3-53
17-15
Link Following Q Data
The serial data word, or link, following the Q data word is selected using Table 12
(see Output Section).
14-12
Link Following
Magnitude Data
The serial data word, or link, following the MAG data word is selected using Table 12
(see Output Section).
11-9
Link Following Phase
Data
The serial data word, or link, following the PHAS data word is selected using Table 12
(see Output Section).
8-6
Link Following
Frequency Data
The serial data word, or link, following the FREQ data word is selected using Table 12
(see Output Section).
5-3
Link Following AGC
Level Data
The serial data word, or link, following the AGC data word is selected using Table 12
(see Output Section).
2-0
Link Following Timing
Error Data
The serial data word, or link, following the TIMER data word is selected using Table 12
(see Output Section).
CONTROL WORD 20: BUFFER RAM, DIRECT PARALLEL, AND DIRECT SERIAL OUTPUT CONFIGURATION
(SYNCHRONIZED WITH PROCCLK)
BIT
POSITION
FUNCTION
DESCRIPTION
31-26
Reserved
Reserved.
25
Data Source for Least
Significant Bytes of
AOUT and BOUT
Output LSBytes, bits (7:0), of AOUT and BOUT can provide:
0- Buffer RAM Mode Output or,
1- Parallel Direct Mode Output.
24
Buffered Output Mode
Interface
Buffered Mode Output interfaces to either:
0- 8-bit
μ
P (address =
μ
P ASEL(5:#); CLK =
μ
P RAM read).
1- 16-bit
μ
P (address = SEL(2:0); CLK = OEBL).
23-22
AOUT Direct Parallel
Output Mode Data
Source
The data word sent by the Direct Parallel Output Mode to AOUT is:
00- I Data. (2’s complement)
01- Magnitude. (O; unsigned binary)
1X- Frequency. (2’s complement)
21-20
BOUT Direct Parallel
Output Mode Data
Source
The data word sent by the Direct Parallel Output Mode to BOUT is:
00- Q Data (2’s complement).
01- Phase (2’s complement).
1X- Magnitude (O; unsigned binary).
19
Serial Output Sync Po-
larity
0- Normal Sync Mode (active high).
1- Sync Inverted (active low).
18
Serial Output Clock
Polarity
0- Output Clock Inverted rising edge aligns with data transitions.
1- Output Clock Normal falling edge aligns with data transitions.
17
Serial Output Sync Po-
sition
0- Sync is asserted one bit time after the last bit of the serial word (Late Mode).
1- Sync is asserted one bit time prior to the first bit of the serial word (Early Mode).
16-14
Serial Out Clock
Divider
000- Serial Output at PROCCLK/16.
001- Serial Output at PROCCLK/8.
010- Serial Output at PROCCLK/4.
011- Serial Output at PROCCLK/2.
1XX- Serial Output at PROCCLK rate.
13-12
I Data Serial Output
Tag Bit
00- No Tag Bit. LSB of word is passed.
01- 0 Tag Bit. LSB of word is set to zero.
1X- 1 Tag Bit. LSB of word is set to one.
CONTROL WORD 19: SERIAL OUTPUT ORDER (SYNCHRONIZED TO PROCCLK) (CONTINUED)
BIT
POSITION
FUNCTION
DESCRIPTION
0
1
HSP50214B