- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383075 > HSP50214AVC (HARRIS SEMICONDUCTOR) Programmable Downconverter PDF資料下載
參數(shù)資料
| 型號： | HSP50214AVC |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Programmable Downconverter |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP120 |
| 文件頁數(shù)： | 3/60頁 |
| 文件大?。?/td> | 467K |
| 代理商： | HSP50214AVC |
第1頁第2頁當(dāng)前第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁
3
Pin Descriptions
NAME
TYPE
DESCRIPTION
V
CC
GND
-
Positive Power Supply Voltage.
-
Ground.
CLKIN
I
Input Clock. This clock should be a multiple of the input sample rate. All input section processing oc-
curs on the rising edge of CLKIN. The frequency of CLKIN is designated f
CLKIN
.
Input Data. The format of the input data may be set to offset binary or 2’s complement. IN13 is the
MSB (see Control Word 0).
IN(13:0)
I
ENI
I
Input Enable. Active Low. This pin enables the input to the part in one of two modes, gated or inter-
polated (see Control Word 0). In gated mode, one sample is taken per CLKIN when ENI is asserted.
The input sample rate is designated f
S
, which can be different from f
CLKIN
When ENI is used.
GAINADJ Input. Adds an offset to the gain via the shifter following the mixer. GAINADJ value is added
to the shift code from the microprocessor (
μ
P) interface. The shift code is saturated to a maximum
code of F. The gain is offset by (6dB)(GAINADJ); (000 = 0dB gain adjust; 111 = 42dB gain adjust)
GAINADJ2 is the MSB. See “Using the Input Gain Adjust Control Signals” Section.
GAINADJ(2:0)
I
PROCCLK
I
Processing Clock. PROCCLK is the clock for all processing functions following the CIC Section. Pro-
cessing is performed on PROCCLK’s rising edge. All output timing is derived from this clock.
NOTE: This clock may be asynchronous to CLKIN.
AGCGNSEL
I
AGC Gain Select. This pin selects between two AGC loop gains. This input is setup and held relative
to PROCCLK. Gain setting 1 is selected when AGCGNSEL = 1.
COF
I
Carrier Offset Frequency Input. This serial input pin is used to load the carrier offset frequency into the
Carrier NCO (see Serial Interface Section). The offset may be 8, 16, 24, or 32 bits. The setup and hold
times are relative to CLKIN. This input is compatible with the output of the HSP50210 Costas loop [1].
COFSYNC
I
Carrier Offset Frequency Sync. This signal is asserted one CLK before the most significant bit (MSB)
of the offset frequency word (see Serial Interface Section). The setup and hold times are relative to
CLKIN. This input is compatible with the output of the HSP50210 Costas loop [1].
SOF
I
Re-Sampler Offset Frequency Input. This serial input pin is used to load the offset frequency into the
Re-Sampler NCO (see Serial Interface Section). The offset may be 8, 16, 24, or 32 bits. The setup
and hold times are relative to PROCCLK. This input is compatible with the output of the HSP50210
Costas loop [1].
SOFSYNC
I
Re-Sampler Offset Frequency Sync. This signal is asserted one CLK before the MSB of the offset
frequency word (see Serial Interface Section). The setup and hold times are relative to PROCCLK.
This input is compatible with the output of the HSP50210 Costas loop [1].
AOUT(15:0)
O
Parallel Output Bus A. Two parallel output modes are available on the HSP50214A. The first is called
the Direct Output Port, where the source is selected through Control Word 20 (see the Microproces-
sor Write Section) and comes directly from the Output MUX Section (see Output Control Section).
The most significant byte of AOUT always outputs the most significant byte of the Parallel Direct Out-
put Port whose data type is selected via
μ
P interface. AOUT15 is the MSB. In this mode, the
AOUT(15:0) bus is updated as soon as data is available. DATARDY is asserted to indicate new data.
The second mode for parallel data is called the Buffer RAM Output Port. The Buffer RAM Output Port
acts like a FIFO for blocks of information called data sets. Within a data set is I, Q, magnitude, phase,
and frequency information; a data type is selected using SEL(2:0). Up to 7 data sets are stored in the
Buffer RAM Output Port. The LSBytes of the AOUT and BOUT busses form the 16 bits for the buffered
output mode and can be used for buffered mode while the MSBytes are outputting data in the direct
output mode.
BOUT(15:0)
O
Parallel Output Bus B. Two parallel output modes are available on the HSP50214A. The first is called
the Direct Output Port, where the source is selected through Control Word 20 (see the Microproces-
sor Write Section) and comes directly from the Output MUX Section (see Output Control Section).
The most significant byte of BOUT always outputs the most significant byte of the Parallel Direct Out-
put Port whose data type is selected via
μ
P interface. BOUT15 is the MSB. In this mode, the
BOUT(15:0) bus is updated as soon as data is available. DATARDY is asserted to indicate new data.
The second mode for parallel data is called the Buffer RAM Output Port. The Buffer RAM Output Port
acts like a FIFO for blocks of information called data sets. Within a data set is I, Q, magnitude, phase,
and frequency information; a particular information is selected using SEL(2:0). Up to 7 data sets is
stored in the Buffer RAM Output Port. The least significant byte of BOUT can be used to either output
the least significant byte of the B Parallel Direct Output Port or the least significant byte of the Buffer
RAM Output Port. See Output Section.
HSP50214A
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HSP50214AVI | Programmable Downconverter |
| HSP50214B | Programmable Downconverter |
| HSP50214BVC | Programmable Downconverter |
| HSP50214BVI | Programmable Downconverter |
| HT84 | ADSL Coupling Transformers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HSP50214AVI | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Programmable Downconverter |
| HSP50214B | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Programmable Downconverter |
| HSP50214B_07 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Programmable Downconverter |
| HSP50214BVC | 功能描述:上下轉(zhuǎn)換器 120L MQFP COMTEMP 14-BIT PROGRAMMABLE DOWNCONVERTER 65MSPS RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| HSP50214BVCZ | 功能描述:上下轉(zhuǎn)換器 120L MQFP COMTEMP 14-BIT PROG DWNCNVRT RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。