28
The programmable parameters for the Timing NCO include
an Enable External Timing NCO Sync (Control Word 11, Bit
5), the serial word width, Number of Offset Frequency Bits
(Control Word 11, Bits 3-4), an Enable Offset Frequency
control (Control Word 11, Bit 2), a Clear NCO Accumulator
control (Control Word 11, Bit 1), a Timing NCO Phase Accu-
mulator Load On Update control (Control Word 11, Bit 0), the
Timing NCO Center Frequency (Control Word 12), a Timing
Phase Offset (Control Word 13, Bits 0-7), a Timing Fre-
quency Strobe (Control Word 14) and a Timing Phase
Strobe (Control Word 15). Refer to the Carrier Synthesizer
Mixer Section for a detailed discussion of the serial interface
for the Timing NCO offset frequency word.
A timing error detector is provided for measuring the phase
difference between the timing NCO and a external clock input,
REFCLK. Timing Error is generated by comparing the values
of two programmable counters. One counter is clocked with
the Timing NCO carry out and the other is clocked by the
REFCLK. The 12-bit NCO Divide parameter is set in Control
Word 18, Bits 16-27. The NCO Divide parameter is the pre-
load to the counter that is clocked by the Timing NCO carry
out. The 12-bit Reference Divide parameter is set in Control
Word 18, Bits 0-11, and is the preload for the counter that is
clocked by the Reference clock. Figure 26 details the block
diagram of the timing error generation circuit. The 16 bits of
timing error are available both as a PDC serial output and as a
processor read parameter. See the Processor Read Section
for more details on accessing this value.
Figure 27A illustrates an application where the Timing Error
Generator is used to lock the receiver samples with a trans-
mit data rate. In this example, the receive samples are at
four times the transmit data rate. An external loop filter is
required, whose frequency error output is fed into the Timing
NCO. This allows the loop to track out the long term drift
between the receive sample rate and the transmit data clock.
SHIFT REG
SYNC
SOF
SOFSYNC
TIMING NCO CENTER
FREQUENCY
TIMING NCO
PHASE OFFSET
32
32
8
MUX
0
MUX
0
CLEAR
PHASE
ACC
PHASE
ACCUMULATOR
SCF
SOF
ENABLE SOF
REG
REG
+
Controlled via microprocessor interface.
5
TIMING PHASE STROBE
TIMING FREQ
STROBE
NUMBER OF SOF BITS
+
R
TIMING NCO
PH ACC
LOAD ON
UPDATE
R
REG
SYNC
SYNCIN2
EN EXT TIMING NCO SYNC
SYNC
CARRY OUT = RUN
FILTER STROBE
FILTER PHASE
SELECT
FIGURE 26. TIMING NCO BLOCK DIAGRAM
REG
Controlled via microprocessor interface.
FIGURE 27. TIMING ERROR GENERATION
PROGRAMMABLE
DIVIDER
PROGRAMMABLE
DIVIDER
REFERENCE
DIVIDE
TE(15:0)
C
REFCLK
R
+
TIMING
NCO
ACC.
P
NCO DIVIDE
(NCO DIVIDE)/2
-
12
4
EN
Controlled via microprocessor interface.
FIGURE 27A. TIMING ERROR APPLICATION
PROGRAMMABLE
DIVIDER
PROGRAMMABLE
DIVIDER
REFERENCE
DIVIDE = N
TE(15:0)
C
Tx DATA CLK
(REFCLK)
R
+
TIMING
NCO
ACC.
P
NCO DIVIDE = 4N
(NCO DIVIDE)/2
-
12
4
EN
LOOP
FILTER
μ
P
TO Tx BLOCK
(MODULATOR)
CLKIN/R
T
R
T
= TOTAL DECIMATION (CIC, HB FILTERS AND FIR)
HSP50214A