參數(shù)資料
型號(hào)： HSP50214AVC
廠商： HARRIS SEMICONDUCTOR
元件分類(lèi)： 通信及網(wǎng)絡(luò)
英文描述： Programmable Downconverter
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP120
文件頁(yè)數(shù)： 23/60頁(yè)
文件大?。?/td> 467K
代理商： HSP50214AVC
23
For example, if M
LG
= 0101 and E
LG
= 1100, the AGC Loop
Gain = 0.3125*2
-7
. The loop gain mantissas and exponents
are set in the AGC Loop Parameter Control Register (Control
Word 8, Bits 0-15).
Two AGC loop gains are provided in the Programmable Down
Converter, for quick adjustment of the AGC loop. The AGC
Gain select is a control input to the device, selecting Gain 0
when AGCGNSEL = 0, and selecting Gain 1 when
AGCGNSEL = 1.
In the HSP50214, a reset event (caused by SYNCIN2 or
CW25) would clear the AGC loop filter accumulator. In the
HSP50214A, if Control Word 27, Bit 15 is set to zero, the
AGC loop filter accumulator will clear as in the original
HSP50214. If Control Word 27, Bit 15 is set to a one, the
backend reset (from CW25) will not clear the AGC loop filter
accumulator.
In the HSP50214, the settling mode of the AGC forces the
mean of the signal magnitude error to zero. The gain error is
scaled and used to adjust the gain up or down. This propor-
tional scaling mode causes the AGC to settle to the final gain
value asymptotically. This AGC settling mode is preferred in
many applications because the loop gain adjustments get
smaller and smaller as the loop settles, reducing any AM dis-
tortion caused by the AGC.
With this AGC settling mode, the proportional gain error
causes the loop to settle more slowly if the threshold is
small. This is because the maximum value of the threshold
minus the magnitude is smaller. Also, the settling can be
asymmetric, where the loop may settle faster for “over range”
signals than for “under range” signals (or vice versa).
In some applications, such as burst signals or TDMA signals,
a very fast settling time and/or a more predictable settling
time is desired. The AGC may be turned off or slowed down
after an initial AGC settling period.
To minimize the settling time, a median AGC settling mode
has been added to the HSP50214A. This mode uses a fixed
gain adjustment with only the direction of the adjustment
controlled by the gain error. This makes the settling time
independent of the signal level.
For example, if the loop is set to adjust 0.5dB per output
sample, the loop gain can slew up or down by 16dB in 16
symbol times, assuming a 2 samples per symbol output
sample rate. This is called a median settling mode because
the loop settles to where there is an equal number of magni-
tude samples above and below the threshold. The disadvan-
tage of this mode is that the loop will have a wander (dither)
equal to the programmed step size. For this reason, it is
advisable to set one loop gain for fast settling at the begin-
ning of the burst and the second loop gain for small adjust-
ments during tracking.
The median settling mode is enabled by setting Control
Word 27, Bit 16 to a logic one. If Control Word 27, Bit 16 is
zero, the mean loop settling mode is selected and the loop
works identically to the HSP50214.
In the median mode, the loop works as follows:
The sign of the true gain error selects a fixed gain error of
0010000000000
b
or 1110000000000
b
.
These gain error values are scaled by the programmable
AGC loop gains to adjust the data path gain.
The maximum slew rate is ~1.5dB per output sample. See
Equation 18.
In order to fully evaluate the dynamic range of the PDC,
Table 9B is provided, which details the bit weighting from the
input to the AGC Multiplier.
Re-Sampler/Halfband Filter
The re-sampler is an NCO controlled polyphase filter that
allows the output sample rate to have a non-integer relation-
ship to the input sample rate. The filter engine can be viewed
conceptually as a fixed interpolation filter, followed by an
NCO controlled decimator.
TABLE 7. AGC LOOP GAIN BINARY MANTISSA TO GAIN
SCALE FACTOR MAPPING
BINARY
CODE
(MMMM)
SCALE
FACTOR
BINARY
CODE
(MMMM)
SCALE
FACTOR
0000
0.0000
1000
0.5000
0001
0.0625
1001
0.5625
0010
0.1250
1010
0.6250
0011
0.1875
1011
0.6875
0100
0.2500
1100
0.7500
0101
0.3125
1101
0.8125
0110
0.3750
1110
0.8750
0111
0.4375
1111
0.9375
TABLE 8. AGC LOOP GAIN BINARY EXPONENT TO GAIN
SCALE FACTOR MAPPING
BINARY
CODE
(EEEE)
SCALE
FACTOR
BINARY
CODE
(EEEE)
SCALE
FACTOR
0000
2
15
1000
2
7
0001
2
14
1001
2
6
0010
2
13
1010
2
5
0011
2
12
1011
2
4
0100
2
11
1100
2
3
0101
2
10-
1101
2
2
0110
2
9
1110
2
1
0111
2
8
1111
2
0
HSP50214A
相關(guān)PDF資料
PDF描述
HSP50214AVI Programmable Downconverter
HSP50214B Programmable Downconverter
HSP50214BVC Programmable Downconverter
HSP50214BVI Programmable Downconverter
HT84 ADSL Coupling Transformers
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HSP50214AVI 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:Programmable Downconverter
HSP50214B 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:Programmable Downconverter
HSP50214B_07 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:Programmable Downconverter
HSP50214BVC 功能描述:上下轉(zhuǎn)換器 120L MQFP COMTEMP 14-BIT PROGRAMMABLE DOWNCONVERTER 65MSPS RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128
HSP50214BVCZ 功能描述:上下轉(zhuǎn)換器 120L MQFP COMTEMP 14-BIT PROG DWNCNVRT RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128
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