參數(shù)資料
型號: HSP50016JC-75
廠商: INTERSIL CORP
元件分類: 數(shù)字信號處理外設(shè)
英文描述: Digital Down Converter
中文描述: 16-BIT, DSP-MIXER, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 5/31頁
文件大?。?/td> 209K
代理商: HSP50016JC-75
3-202
Phase Generator Block Diagram
Functional Description
The primary function of the DDC is to extract a narrow
frequency band of interest from a wideband input, convert that
band to baseband and output it in either a quadrature or real
form. This narrow band extraction is accomplished by down
converting and centering the band of interest at DC. The
conversion is done by multiplying the input data with a
quadrature sinusoid. A quadrature lowpass filter is applied to
the multiplier outputs. Identical real lowpass filters are
provided in the in-phase (I) and quadrature phase (Q)
processing branches. Each filtering chain consists of a
cascaded HDF and FIR filter, which extracts the band of
interest. During filtering, the signal is decimated by a rate
which is proportional to the output bandwidth. The bandwidth
of the resulting signal is the double sided passband width of
the lowpass filters. An Output Formatter manipulates the filter
output to provide the data in a variety of serial data formats.
MAXIMUM PHASE
INCREMENT
DELTA PHASE
INCREMENT
MINIMUM PHASE
INCREMENT
33
32
18
32
32
MODE
CONTROL
C
PHASE WORD
(TO THE
SIN/COS
GENERATOR)
18
MUX SELECT 0
MUX SELECT 1
CONTROL
PHASE
INCREMENT
REGISTER
33
A
-
INITIALIZE
PHASE INCR.
TO MIN
INITIALIZE
PHASE INCR.
TO MAX
PHASE ADDER
CARRY OUT
FIGURE 2. PHASE GENERATOR BLOCK DIAGRAM
Indicates parameters set in Control Registers.
PHASE OFFSET
>
M
0
2
R
E
G
>
R
E
G
>
R
E
G
>
R
E
G
>
0
M
+
PHASE ACCUMULATOR
PHASE REGISTER
R
E
G
>
R
E
G
>
ADDER /
SUBTRACTOR
MUX SELECT 0
MUX SELECT 1
PHASE INCREMENT ACCUMULATOR
+
HSP50016
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