參數(shù)資料
型號： HSP50016JC-75
廠商： INTERSIL CORP
元件分類： 數(shù)字信號處理外設
英文描述： Digital Down Converter
中文描述： 16-BIT, DSP-MIXER, PQCC44
封裝： PLASTIC, LCC-44
文件頁數(shù)： 11/31頁
文件大?。?/td> 209K
代理商： HSP50016JC-75
3-208
The coefficients of the filter are quantized to 22 bits to
preserve greater than 106dB of stopband attenuation. The
sum of products of each filter output calculation is a 38-bit
number with 37 fractional bits.
When a quadrature output is selected, the outputs of the
FIR filters are decimated by a factor of four. When real
output is selected, only the I output is active. The output is
decimated by two in this case. When Filter Only Mode is
selected, only the I filter path is active and its output is
decimated by four.
The composite filter bandwidths are a function of the HDF
decimation rate and the FIR Filter shape. The double sided
bandwidths are specified by Equations 10 and 11
.
where F
S
= CLK; R = HDF Decimation Factor.
The single sided bandwidths are specified in Equations 12
and 13.
where F
S
= CLK; R = HDF Decimation Factor.
NOTE: The output data rate of the FIR is the HDF output
rate divided by either 2 or 4, depending on mode. Recall
the HDF output rate is CLK/R. (See Table 1.)
Output Formatter
The circuit has two serial data outputs, I and Q. The timing
of the output bits is referenced to IQCLK and IQSTB. There
are several modes of operation for the data and control line
interface, all of which were designed to be compatible with
common microprocessors. These interface modes are
selected by loading the appropriate control words (see
Tables 3 through 10, with Table 9 containing most interface
parameters).
Quadrature data output can occur in one of two ways:
simultaneously or sequentially. The simultaneous method
clocks out the I and Q data on their respective serial output
pins. The I followed by Q method clocks I and Q out
sequentially on the I output pin: the entire I word is serially
clocked out first, then the entire Q word. In real data Output
Mode, the Formatter converts the quadrature data to real
and clocks it out serially on the I output pin. In all modes, the
I and Q outputs return to the zero state after the last bit is
transmitted.
When the “I followed by Q” signal (CW6, bit 35) is low,
I data will appear on the I output and Q data will appear on
the Q output.
When the “I followed by Q” signal (CW6, bit 35) is asserted,
the Q output is inactive and I data, followed by Q data
appear on the I output. When in this state, and both the “Test
Enable” signal (CW1, Bit 3), and “Q Strobe on Rollover”
signal (CW7, Bit 10) signal are asserted, the Phase
FIGURE 9. FIR COMPENSATION FOR HDF ROLL OFF (FOR R = 16)
M
0.5
-0.5
FREQUENCY (Hz)
f
S
16R
3f
S
64R
f
S
32R
f
S
64R
0.4
0.3
0.2
0.1
0
COMPOSITE
HDF/FIR
FIR
HDF
-0.1
-0.2
-0.3
-0.4
3dB BW
DS
0.1375F
S
R
=
–
(EQ. 10)
16 < R < 16384
102dB BW
DS
0.2002F
S
R
=
–
(EQ. 11)
16 < R < 16384
3dB BW
SS
0.06875F
S
R
=
–
(EQ. 12)
102dB BW
SS
0.100097F
S
R
=
–
(EQ. 13)
TABLE 1. FIR OUTPUT RATE AND DECIMATION
OUTPUT MODE
FIR OUTPUT RATE
FIR DECIMATION
Real
CLK/2R
2
Complex
CLK/4R
4
Filter Only
CLK/4R
4
R - HDF Decimation Factor
HSP50016
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