參數(shù)資料
型號: HSP50016JC-75
廠商: INTERSIL CORP
元件分類: 數(shù)字信號處理外設(shè)
英文描述: Digital Down Converter
中文描述: 16-BIT, DSP-MIXER, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 4/31頁
文件大?。?/td> 209K
代理商: HSP50016JC-75
3
DDC Functional Block Diagram
PHASE
GENERATOR
COEFFICIENT
ROM
MULTIPLIER/
ACCUMULATOR
FORMATTER
Q
CCLK
I
DECODER
IQCLK
IQSTB
18
DATA0-15
FIR SECTION
HDF
SCALING
MULTIPLIER
CSTB
CS
CDATA
RESET
TDO
TCLK
TMS
TDI
TRST
TEST ACCESS PORT
18
SCALE
FACTOR
IQSTRT
CLK
MULTIPLIER/
ACCUMULATOR
DATA
RAM
HDF
INPUT
REGISTER
IEEE 1149.1
MIXER
SECTION
SECTION
LOCAL OSCILLATOR
SHIFTER
CONTROL
BUFFERS
CONTROL
REGISTERS
0
1
2
7
1
2
7
D
Q
D
Q
22
SHIFT
REGISTER
PHASE WORD
SIN
COS
+
+
17
17
18
18
17
17
17
17
18
16
SIN/COS
GENERATOR
DATA
RAM
HDF
SHIFTER
SHIFT
REGISTER
FIGURE 1. FUNCTIONAL BLOCK DIAGRAM
CLK
SER
= IQCLK
CLK
CLK
R
(PARALLEL
TO SERIAL
CONVERTER
AND BUFFER)
INPUT
FORMAT
MIN PHASE INCR
DELTA PHASE INCR
PHASE OFFSET
MAX PHASE INCR
MODE
HDF
SHIFT
SCALING
MULTIPLIER
GAIN
WAIT FOR RAM FULL
OUTPUT FORMAT
TIME SLOT LENGTH
NUMBER OF OUTPUT BITS
OUTPUT SENSE
I FOLLOWED BY Q
TIME SLOT NUMBER
IQCLK POLARITY
IQCLK DUTY CYCLE
IQCLK DURATION
IQCLK THREE-STATE CTL
IQSTRB POLARITY
IQSTRB LOCATION
IQSTRB THREE-STATE CTRL
I POLARITY AND THREE-STATE CTRL
Q POLARITY AND THREE-STATE CTRL
IQ CLK RATE
TEST ENABLE AND CONTROL SIGNALS
Indicates parameters from control registers.
CONTROL
PARAMETERS
HDF
DECIMATION
COUNTER PRELOAD (DCP)
CLK
4R
H
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