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參數(shù)資料
| 型號(hào)： | HSP50016JC-75 |
| 廠商： | INTERSIL CORP |
| 元件分類： | 數(shù)字信號(hào)處理外設(shè) |
| 英文描述： | Digital Down Converter |
| 中文描述： | 16-BIT, DSP-MIXER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 26/31頁 |
| 文件大?。?/td> | 209K |
| 代理商： | HSP50016JC-75 |
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3-223
Figure 21 shows a Block Diagram of this configuration. The
DDCs are configured by the microprocessor by first writing a
logical 0 to its Chip Select line. The control words are written
to that part in any order. When the part has been configured,
CS is written high again, and the next part is configured in
the same manner. Collisions are prevented by programming
each DDC with a unique Time Slot number, which holds its
output from 0 to 63 output word times before transmission.
Each part also has a Time Slot Length, whose minimum
value is given in Equation 8. Note that a value greater than
the minimum can be used to give the processor time to
operate on the data
The corresponding Configuration Register setup is similar to
that of single channel down conversion, except for the Auto
Three-State fields. In this example, the first DDC in the chain
is set to drive IQCLK; the others have this output set for high
impedance. (It makes no difference which DDC is chosen to
be the one to drive IQCLK, but it must be active
continuously). The unused outputs are put in their high
impedance condition on the other DDCs to minimize power
consumption. Note also that this example shows all DDCs in
I followed by Q Mode so that only one data line to the
microprocessor is necessary. Figure 22 gives the timing of
the output data.
When operating a set of HSP50016s in the Multiple
Channel Operation Mode, the two control signals that
ensure proper time slot operation are: CS and RESET. The
CS allows unique Control Word loading of each DDC. The
RESET synchronizes all of the DDC’s to the start of the first
time slot.
NOTE:
DDC’s would be programmed identically, except for the
NCO (L.O.) frequency and Time Slot Number. This implies
identical HDF Decimation factors, Time Slot Length’s,
Number of Output Bits, Output Mode are identical in all
DDCs. This means that the output rate of all DDC HDFs,
FIRs and Parallel to Serial Converters are identical.
In this mode, it was anticipated that parallel
The DDC keeps an internal count of the number of IQCLK
periods that have transpired since the rising edge of RESET.
The internal counter of each DDC is set to enable the serial
output at the time slot number assigned to that DDC. The
count is based on the time slot length, number of output bits,
HDF decimation, and Output Mode programmed to that part.
NOTE: In the Multiple Channel Operation Mode, all the
time slot lengths should be set to the same value to avoid
output signal contention. The time slot length should be
equal to the largest “minimum time slot length” as calcu-
lated by Equation 15, for every DDC in the multichannel
arrangement. Note that Equation 8 is in IQCLK periods, not
CLK periods. Equations 7 and 9 will be helpful in making
the translation to CLK periods.
This mode does not require that all of the time slots be used
(assigned to a DDC). If only two parts were used and the
maximum time signal isolation was desired, one could
assign the first signal time slot 31 and the second signal time
slot 63. This would ensure that the maximum separation in
time occurred. It is the designers responsibility to ensure that
the output rate, including the decimation is consistent with
the time allotted to output each signal.
HSP50016
MICROPROCESSOR
I
IQCLK
IQSTB
IQSTRT
CDATA
CCLK
CSTB
CS
HSP50016
I
IQCLK
IQSTB
IQSTRT
CDATA
CCLK
CSTB
CS
A0-15
DATA0-15
CLK
DATA0-15
CLK
DATA
FROM A/D
SYSTEM
CLOCK
OSCILLATOR
CHIP SELECT
DECODER
R/W
STRB
DX
CLKX
FSX
DR
CLKR
FSR
FIGURE 21. CIRCUIT FOR MULTIPLE CHANNEL OPERATION
(AUTO THREE-STATE)
DDC 0
DDC 1
DDC N-1
TIME SLOT 0
TIME SLOT 1
TIME SLOT N-1
FIGURE 22. TIMING FOR MULTIPLE CHANNEL OPERATION
(AUTO THREE-STATE)
HSP50016
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