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參數(shù)資料
| 型號： | GS8162V18AGB-350I |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | SRAM |
| 英文描述： | 1M X 18 CACHE SRAM, 4.5 ns, PBGA119 |
| 封裝： | PLASTIC, BGA-119 |
| 文件頁數(shù)： | 1/37頁 |
| 文件大小： | 947K |
| 代理商： | GS8162V18AGB-350I |
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Rev: 1.00a 6/2003
1/37
2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
ByteSafe is a Trademark of Giga Semiconductor, Inc. (GSI Technology).
GS8162V18A(B/D)/GS8162V36A(B/D)/GS8162V72A(C)
1M x 18, 512K x 36, 256K x 72
18Mb S/DCD Sync Burst SRAMs
350 MHz–150 MHz
1.8 V VDD
1.8 V I/O
119-, 165- & 209-Pin BGA
Commercial Temp
Industrial Temp
Preliminary
Features
FT pin for user-configurable flow through or pipeline operation
Single/Dual Cycle Deselect selectable
IEEE 1149.1 JTAG-compatible Boundary Scan
ZQ mode pin for user-selectable high/low output drive
1.8 V +10%/–10% core power supply
LBO pin for Linear or Interleaved Burst mode
Internal input resistors on mode pins allow floating mode pins
Default to SCD x18/x36 Interleaved Pipeline mode
Byte Write (BW) and/or Global Write (GW) operation
Internal self-timed write cycle
Automatic power-down for portable applications
JEDEC-standard 119-, 165-, and 209-bump BGA package
Functional Description
Applications
The GS8162V18A(B/D)/GS8162V36A(B/D)/GS8162V72A(C) is an
18,874,368-bit high performance synchronous SRAM with a 2-bit
burst address counter. Although of a type originally developed for
Level 2 Cache applications supporting high performance CPUs, the
device now finds application in synchronous SRAM applications,
ranging from DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enable (E1), address burst control inputs
(ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are
synchronous and are controlled by a positive-edge-triggered clock
input (CK). Output enable (G) and power down control (ZZ) are
asynchronous inputs. Burst cycles can be initiated with either ADSP
or ADSC inputs. In Burst mode, subsequent burst addresses are
generated internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or interleave order
with the Linear Burst Order (LBO) input. The Burst function need not
be used. New addresses can be loaded on every cycle with no
degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by the user
via the FT mode . Holding the FT mode pin low places the RAM in
Flow Through mode, causing output data to bypass the Data Output
Register. Holding FT high places the RAM in Pipeline mode,
activating the rising-edge-triggered Data Output Register.
SCD and DCD Pipelined Reads
The GS8162V18A(B/D)/GS8162V36A(B/D)/GS8162V72A(C) is an
SCD (Single Cycle Deselect) and DCD (Dual Cycle Deselect)
pipelined synchronous SRAM. DCD SRAMs pipeline disable
commands to the same degree as read commands. SCD SRAMs
pipeline deselect commands one stage less than read commands. SCD
RAMs begin turning off their outputs immediately after the deselect
command has been captured in the input registers. DCD RAMs hold
the deselect command for one full cycle and then begin turning off
their outputs just after the second rising edge of clock. The user may
configure this SRAM for either mode of operation using the SCD
mode input.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable (BW)
input combined with one or more individual byte write signals (Bx).
In addition, Global Write (GW) is available for writing all bytes at one
time, regardless of the Byte Write control inputs.
FLXDrive
The ZQ pin allows selection between high drive strength (ZQ low) for
multi-drop bus applications and normal drive strength (ZQ floating or
high) point-to-point applications. See the Output Driver
Characteristics chart for details.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High) of
the ZZ signal, or by stopping the clock (CK). Memory data is retained
during Sleep mode.
Core and Interface Voltages
The GS8162V18A(B/D)/GS8162V36A(B/D)/GS8162V72A(C)
operates on a 1.8 V power supply. All input are 1.8 V compatible.
Separate output power (VDDQ) pins are used to decouple output noise
from the internal circuits and are 1.8 V compatible.
Parameter Synopsis
-350
-333
-300
-250
-200
-150
Unit
Pipeline
3-1-1-1
tKQ (x18/x36)
tKQ (x72)
tCycle
1.8
2.0
2.85
2.0
2.2
3.0
2.2
2.5
3.3
2.3
2.6
4.0
2.7
2.8
5.0
3.3
6.7
ns
Curr (x18)
Curr (x32/x36)
Curr (x72)
395
455
—
370
430
—
335
390
495
280
330
425
230
270
345
185
210
270
mA
Flow
Through
2-1-1-1
tKQ
tCycle
4.5
4.7
5.0
5.5
6.5
7.5
ns
Curr (x18)
Curr (x32/x36)
Curr (x72)
270
305
—
250
285
—
230
270
345
210
240
315
185
205
275
170
190
250
mA
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相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS8162V72CC-150 | 制造商:GSI Technology 功能描述:SRAM SYNC SGL 1.8V 18MBIT 256KX72 7.5NS/3.8NS 209BGA - Trays |
| GS8162V72CC-150I | 制造商:GSI Technology 功能描述:256K X 72 (18 MEG) SYNCH BURST, SCD, JTAG, FLEXDRIVE - Trays |
| GS8162Z18BB-150 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 18MBIT 1MX18 7.5NS/3.8NS 119FBGA - Trays |
| GS8162Z18BB-150I | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 18MBIT 1MX18 7.5NS/3.8NS 119FBGA - Trays |
| GS8162Z18BB-150IV | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V/2.5V 18MBIT 1MX18 7.5NS/3.8NS 119FPBGA - Trays |
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