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參數資料
| 型號： | GS8162ZV36AGD-350I |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | SRAM |
| 英文描述： | 512K X 36 ZBT SRAM, 4.5 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1 MM PITCH, FBGA-165 |
| 文件頁數： | 1/36頁 |
| 文件大?。?/td> | 884K |
| 代理商： | GS8162ZV36AGD-350I |
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Rev: 1.00a 6/2003
1/36
2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
GS8162ZV18A(B/D)/GS8162ZV36A(B/D)/GS8162ZV72A(C)
18Mb Pipelined and Flow Through
Synchronous NBT SRAM
350 MHz–150 MHz
1.8 V VDD
1.8 V I/O
119, 165, & 209 BGA
Commercial Temp
Industrial Temp
Preliminary
Features
NBT (No Bus Turn Around) functionality allows zero wait
Read-Write-Read bus utilization; fully pin-compatible with
both pipelined and flow through NtRAM, NoBL and
ZBT SRAMs
1.8 V +10%/–10% core power supply
1.8 V I/O supply
User-configurable Pipeline and Flow Through mode
ZQ mode pin for user-selectable high/low output drive
IEEE 1149.1 JTAG-compatible Boundary Scan
On-chip write parity checking; even or odd selectable
On-chip parity encoding and error detection
LBO pin for Linear or Interleave Burst mode
Pin-compatible with 2M, 4M, and 8M devices
Byte write operation (9-bit Bytes)
3 chip enable signals for easy depth expansion
ZZ Pin for automatic power-down
JEDEC-standard 119-, 165-, or 209-Bump BGA package
Functional Description
The GS8162ZV18A(B/D)/V36A(B/D)/V72A(C) is an 18Mbit
Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT,
NtRAM, NoBL or other pipelined read/double late write or
flow through read/single late write SRAMs, allow utilization
of all available bus bandwidth by eliminating the need to insert
deselect cycles when the device is switched from read to write
cycles.
Because it is a synchronous device, address, data inputs, and
read/write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8162ZV18A(B/D)/V36A(B/D)/V72A(C) may be
configured by the user to operate in Pipeline or Flow Through
mode. Operating as a pipelined synchronous device, in
addition to the rising-edge-triggered registers that capture input
signals, the device incorporates a rising edge triggered output
register. For read cycles, pipelined SRAM output data is
temporarily stored by the edge-triggered output register during
the access cycle and then released to the output drivers at the
next rising edge of clock.
The GS8162ZV18A(B/D)/V36A(B/D)/V72A(C) is
implemented with GSI's high performance CMOS technology
and is available in a JEDEC-standard 119-bump (x18 & x36),
165-bump (x18 & x36), or 209-bump (x72) BGA package.
Parameter Synopsis
-350
-333
-300
-250
-200
-150
Unit
Pipeline
3-1-1-1
tKQ (x18/x36)
tKQ (x72)
tCycle
1.8
2.0
2.85
2.0
2.2
3.0
2.2
2.5
3.3
2.3
2.6
4.0
2.7
2.8
5.0
3.3
6.7
ns
Curr (x18)
Curr (x32/x36)
Curr (x72)
395
455
—
370
430
—
335
390
495
280
330
425
230
270
345
185
210
270
mA
Flow
Through
2-1-1-1
tKQ
tCycle
4.5
4.7
5.0
5.5
6.5
7.5
ns
Curr (x18)
Curr (x32/x36)
Curr (x72)
270
305
—
250
285
—
230
270
345
210
240
315
185
205
275
170
190
250
mA
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相關代理商/技術參數 |
參數描述 |
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| GS8170DW36AC-300I | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 1.8NS 209FBGA - Trays |
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| GS8170DW36AGC-250 | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 2.1NS 209FBGA - Trays |
| GS8170DW36AGC-250I | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 2.1NS 209FBGA - Trays |
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