參數(shù)資料
型號(hào)： GS8162ZV36AGD-350I
廠商： GSI TECHNOLOGY
元件分類： SRAM
英文描述： 512K X 36 ZBT SRAM, 4.5 ns, PBGA165
封裝： 13 X 15 MM, 1 MM PITCH, FBGA-165
文件頁(yè)數(shù)： 6/36頁(yè)
文件大?。?/td> 884K
代理商： GS8162ZV36AGD-350I
Rev: 1.00a 6/2003
14/36
2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8162ZV18A(B/D)/GS8162ZV36A(B/D)/GS8162ZV72A(C)
Preliminary
Burst Cycles
Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from
read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address
generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when
driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write
the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into
Load mode.
Burst Order
The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been
accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is Low, a linear burst
sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables
below for details.
FLXDrive
The ZQ pin allows selection between NBT RAM nominal drive strength (ZQ low) for multi-drop bus applications and low drive
strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details.
Note:
There arepull-up devices on the ZQ, SCD, and FT pins and pull-down device on the ZZ pin, so those input pins can be unconnected and the chip
will operate in the default states as specified in the above tables.
Enable / Disable Parity I/O Pins
This SRAM allows the user to configure the device to operate in Parity I/O active (x18, x36, or x72) or in Parity I/O inactive (x16,
x32, or x64) mode. Holding the PE bump low or letting it float will activate the 9th I/O on each byte of the RAM.
Mode Pin Functions
Mode Name
Pin
Name
State
Function
Burst Order Control
LBO
L
Linear Burst
H
Interleaved Burst
Output Register Control
FT
L
Flow Through
H or NC
Pipeline
Power Down Control
ZZ
L or NC
Active
H
Standby, IDD = ISB
FLXDrive Output Impedance Control
ZQ
L
High Drive (Low Impedance)
H or NC
Low Drive (High Impedance)
9th I/O Enable
PE
L or NC
Activate 9th I/Os
H
Deactivate 9th I/Os
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