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參數(shù)資料
| 型號： | GS81302D10E-300I |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | SRAM |
| 英文描述： | 16M X 9 DDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1 MM PITCH, FPBGA-165 |
| 文件頁數(shù)： | 6/33頁 |
| 文件大?。?/td> | 687K |
| 代理商： | GS81302D10E-300I |
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Preliminary
GS81302D07/10/19/37E-450/400/350/333/300
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03 12/2010
14/33
2008, GSI Technology
State Diagram
Power-Up
Read NOP
Load New
Read Address
D Count = 0
DDR Read
D Count = D Count + 1
Write NOP
Load New
Write Address
D Count = 0
DDR Write
D Count = D Count + 1
WRITE
READ
D Count = 2
WRITE
D Count = 2
READ
WRITE
Always
READ
D Count = 2
Notes:
1. Internal burst counter is fixed as 2-bit linear (i.e., when first address is A0+0, next internal burst address is A0+1.
2. “READ” refers to read active status with R = Low, “READ” refers to read inactive status with R = High. The same is
true for “WRITE” and “WRITE”.
3. Read and write state machine can be active simultaneously.
4. State machine control timing sequence is controlled by K.
READ
D Count = 1
Always
Increment
Read Address
WRITE
D Count = 2
Increment
Write Address
WRITE
D Count = 1
Always
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| GS81302T10E-350I | 16M X 9 DDR SRAM, 0.45 ns, PBGA165 |
| GS81302T110E-450T | 16M X 9 DDR SRAM, 0.37 ns, PBGA165 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS81302D10E-333 | 制造商:GSI Technology 功能描述:GS81302D10E-333 - Trays |
| GS81302D10E-333I | 制造商:GSI Technology 功能描述:GS81302D10E-333I - Trays |
| GS81302D10E-350 | 制造商:GSI Technology 功能描述:165 FBGA - Bulk |
| GS81302D10E-375 | 制造商:GSI Technology 功能描述:GS81302D10E-375 - Trays |
| GS81302D10E-375I | 制造商:GSI Technology 功能描述:GS81302D10E-375I - Trays |
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