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參數(shù)資料
| 型號： | GS81302D10E-300I |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | SRAM |
| 英文描述： | 16M X 9 DDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1 MM PITCH, FPBGA-165 |
| 文件頁數(shù)： | 1/33頁 |
| 文件大?。?/td> | 687K |
| 代理商： | GS81302D10E-300I |
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Preliminary
GS81302D07/10/19/37E-450/400/350/333/300
144Mb SigmaQuad-II+TM
Burst of 4 SRAM
450 MHz–300 MHz
1.8 V VDD
1.8 V and 1.5 V I/O
165-Bump BGA
Commercial Temp
Industrial Temp
Rev: 1.03 12/2010
1/33
2008, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Features
2.0 clock Latency
Simultaneous Read and Write SigmaQuad Interface
JEDEC-standard pinout and package
Dual Double Data Rate interface
Byte Write controls sampled at data-in time
Burst of 4 Read and Write
On-Die Termination (ODT) on Data (D), Byte Write (BW),
and Clock (K, K) inputs
1.8 V +100/–100 mV core power supply
1.5 V or 1.8 V HSTL Interface
Pipelined read operation
Fully coherent read and write pipelines
ZQ pin for programmable output drive strength
Data Valid Pin (QVLD) Support
IEEE 1149.1 JTAG-compliant Boundary Scan
165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
RoHS-compliant 165-bump BGA package available
SigmaQuad Family Overview
The GS81302D07/10/19/37E are built in compliance with the
SigmaQuad-II+ SRAM pinout standard for Separate I/O
synchronous SRAMs. They are 150,994,944-bit (144Mb)
SRAMs. The GS81302D07/10/19/37E SigmaQuad SRAMs
are just one element in a family of low power, low voltage
HSTL I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Clocking and Addressing Schemes
The GS81302D07/10/19/37E SigmaQuad-II+ SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer.
Because Separate I/O SigmaQuad-II+ B4 RAMs always
transfer data in four packets, A0 and A1 are internally set to 0
for the first read or write transfer, and automatically
incremented by 1 for the next transfers. Because the LSBs are
tied off internally, the address field of a SigmaQuad-II+ B4
RAM is always two address pins less than the advertised index
depth (e.g., the 8M x 18 has a 2M addressable index).
Parameter Synopsis
-450
-400
-350
-333
-300
tKHKH
2.2 ns
2.5 ns
2.86 ns
3.0 ns
3.3 ns
tKHQV
0.45 ns
165-Bump, 15 mm x 17 mm BGA
1 mm Bump Pitch, 11 x 15 Bump Array
Bottom View
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PDF描述 |
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| GS81302T09E-375T | 16M X 9 DDR SRAM, 0.45 ns, PBGA165 |
| GS81302T18E-350T | 8M X 18 DDR SRAM, 0.45 ns, PBGA165 |
| GS81302T10E-350I | 16M X 9 DDR SRAM, 0.45 ns, PBGA165 |
| GS81302T110E-450T | 16M X 9 DDR SRAM, 0.37 ns, PBGA165 |
| GS816136CGD-250T | 512K X 36 CACHE SRAM, 5.5 ns, PBGA165 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS81302D10E-333 | 制造商:GSI Technology 功能描述:GS81302D10E-333 - Trays |
| GS81302D10E-333I | 制造商:GSI Technology 功能描述:GS81302D10E-333I - Trays |
| GS81302D10E-350 | 制造商:GSI Technology 功能描述:165 FBGA - Bulk |
| GS81302D10E-375 | 制造商:GSI Technology 功能描述:GS81302D10E-375 - Trays |
| GS81302D10E-375I | 制造商:GSI Technology 功能描述:GS81302D10E-375I - Trays |
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