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參數(shù)資料
| 型號： | GS81302D10E-300I |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | SRAM |
| 英文描述： | 16M X 9 DDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1 MM PITCH, FPBGA-165 |
| 文件頁數(shù)： | 3/33頁 |
| 文件大小： | 687K |
| 代理商： | GS81302D10E-300I |
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Separate I/O SigmaQuad II+ B4 SRAM Truth Table
Previous
Operation
A
R
W
Current
Operation
D
Q
K
↑
(tn-1)
K
↑
(tn)
K
↑
(tn)
K
↑
(tn)
K
↑
(tn)
K
↑
(tn+1)
K
↑
(tn+1)
K
↑
(tn+2)
K
↑
(tn+2)
K
↑
(tn+2)
K
↑
(tn+2)
K
↑
(tn+3)
K
↑
(tn+3)
Deselect
X
1
Deselect
X
—
Hi-Z
—
Write
X
1
X
Deselect
D2
D3
—
Hi-Z
—
Read
X
1
Deselect
X
—
Q2
Q3
—
Deselect
V
1
0
Write
D0
D1
D2
D3
Hi-Z
—
Deselect
V
0
X
Read
X
—
Q0
Q1
Q2
Q3
Read
V
X
0
Write
D0
D1
D2
D3
Q2
Q3
—
Write
V
0
X
Read
D2
D3
—
Q0
Q1
Q2
Q3
Notes:
1. “1” = input “high”; “0” = input “l(fā)ow”; “V” = input “valid”; “X” = input “don’t care”
2. “—” indicates that the input requirement or output state is determined by the next operation.
3. Q0, Q1, Q2, and Q3 indicate the first, second, third, and fourth pieces of output data transferred during Read operations.
4. D0, D1, D2, and D3 indicate the first, second, third, and fourth pieces of input data transferred during Write operations.
5. Users should not clock in metastable addresses.
Preliminary
GS81302D07/10/19/37E-450/400/350/333/300
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03 12/2010
11/33
2008, GSI Technology
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PDF描述 |
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| GS81302T10E-350I | 16M X 9 DDR SRAM, 0.45 ns, PBGA165 |
| GS81302T110E-450T | 16M X 9 DDR SRAM, 0.37 ns, PBGA165 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS81302D10E-333 | 制造商:GSI Technology 功能描述:GS81302D10E-333 - Trays |
| GS81302D10E-333I | 制造商:GSI Technology 功能描述:GS81302D10E-333I - Trays |
| GS81302D10E-350 | 制造商:GSI Technology 功能描述:165 FBGA - Bulk |
| GS81302D10E-375 | 制造商:GSI Technology 功能描述:GS81302D10E-375 - Trays |
| GS81302D10E-375I | 制造商:GSI Technology 功能描述:GS81302D10E-375I - Trays |
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