- 您現在的位置：買賣IC網 > PDF目錄173637 > GS81302D10E-300I (GSI TECHNOLOGY) 16M X 9 DDR SRAM, 0.45 ns, PBGA165 PDF資料下載
參數資料
| 型號： | GS81302D10E-300I |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | SRAM |
| 英文描述： | 16M X 9 DDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1 MM PITCH, FPBGA-165 |
| 文件頁數： | 31/33頁 |
| 文件大?。?/td> | 687K |
| 代理商： | GS81302D10E-300I |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁當前第31頁第32頁第33頁
Preliminary
GS81302D07/10/19/37E-450/400/350/333/300
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03 12/2010
7/33
2008, GSI Technology
Background
Separate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are
needed. Therefore, the SigmaQuad-II+ SRAM interface and truth table are optimized for alternating reads and writes. Separate I/O
SRAMs are unpopular in applications where multiple reads or multiple writes are needed because burst read or write transfers from
Separate I/O SRAMs can cut the RAM’s bandwidth in half.
Alternating Read-Write Operations
SigmaQuad-II+ SRAMs follow a few simple rules of operation.
- Read or Write commands issued on one port are never allowed to interrupt an operation in progress on the other port.
- Read or Write data transfers in progress may not be interrupted.
- R and W high always deselects the RAM.
- All address, data, and control inputs are sampled on clock edges.
In order to enforce these rules, each RAM combines present state information with command inputs. See the Truth Table for
details.
SigmaQuad-II+ B4 SRAM DDR Read
The status of the Address Input, W, and R pins are sampled by the rising edges of K. W and R high causes chip disable. A Low on
the Read Enable pin, R, begins a read cycle. R is always ignored if the previous command loaded was a read command. Clocking
in a High on the Read Enable pin, R, begins a read port deselect cycle.
SRAM DDR Write
The status of the Address Input, W, and R pins are sampled by the rising edges of K. W and R High causes chip disable. A Low on
the Write Enable pin, W, and a High on the Read Enable pin, R, begins a write cycle. W is always ignored if the previous command
was a write command. Data is clocked in by the next rising edge of K, the rising edge of K after that, the next rising edge of K, and
finally by the next rising edge of K.
相關PDF資料 |
PDF描述 |
|---|---|
| GS81302T09E-375T | 16M X 9 DDR SRAM, 0.45 ns, PBGA165 |
| GS81302T18E-350T | 8M X 18 DDR SRAM, 0.45 ns, PBGA165 |
| GS81302T10E-350I | 16M X 9 DDR SRAM, 0.45 ns, PBGA165 |
| GS81302T110E-450T | 16M X 9 DDR SRAM, 0.37 ns, PBGA165 |
| GS816136CGD-250T | 512K X 36 CACHE SRAM, 5.5 ns, PBGA165 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| GS81302D10E-333 | 制造商:GSI Technology 功能描述:GS81302D10E-333 - Trays |
| GS81302D10E-333I | 制造商:GSI Technology 功能描述:GS81302D10E-333I - Trays |
| GS81302D10E-350 | 制造商:GSI Technology 功能描述:165 FBGA - Bulk |
| GS81302D10E-375 | 制造商:GSI Technology 功能描述:GS81302D10E-375 - Trays |
| GS81302D10E-375I | 制造商:GSI Technology 功能描述:GS81302D10E-375I - Trays |
發(fā)布緊急采購，3分鐘左右您將得到回復。