參數(shù)資料
型號: GPTRM
英文描述: General-Purpose Timer Reference Manual
中文描述: 通用定時器參考手冊
文件頁數(shù): 62/90頁
文件大?。?/td> 647K
代理商: GPTRM
MOTOROLA
10-4
APPLICATIONS AND EXAMPLES
GPT
REFERENCE MANUAL
10.3 Software Examples
This section contains software that shows how to initialize parts of the GPT. The soft-
ware is interrupt driven. It also shows how to set up the interrupt vectors and adjust
the priority of the different channels in the GPT. Portions of code dealing with calculat-
ing control values for the motor speed were excluded.
Motorola Assembler (3.0) Mon Apr 15 14:04:11 1991
abs. LC obj. code source line
---- ---- --------- -----------
1
|* Example program/programs to show operation of GPT.
2
|* This code written for use on a MC68331 BCC for demonstration
3
|* purposes, but the same basic routines could be used on other
4
|* Motorola modular microcontroller family MCUs.
5
|
6
|*
7
|*
8
|*
9
|*
10
|*
11
|*
12
|*
13
|*
GENERAL REGISTER ADDRESS EQUATES
14
|*
15
|
16
00FF F900
|BASE
EQU
17
|
18
00FF F900
|GMCR
BASE
19
00FF F904
|GICR
EQU
20
00FF F906
|PDDR_PDR
EQU
21
00FF F907
|PDR
EQU
22
00FF F908
|OC1MD
EQU
23
00FF F90A
|TCNT
EQU
24
00FF F90C
|PACTL_PACNTEQU
25
00FF F90E
|TIC1
EQU
26
00FF F910
|TIC2
EQU
27
00FF F912
|TIC3
EQU
28
00FF F914
|TOC1
EQU
29
00FF F916
|TOC2
EQU
30
00FF F918
|TOC3
EQU
31
00FF F91A
|TOC
EQU
32
00FF F91C
|TI4O5
EQU
33
00FF F91E
|TCTL1_2
EQU
34
00FF F920
|TMSK1_2
EQU
35
00FF F922
|TFLG1_2
EQU
36
00FF F923
|TFLG2
EQU
37
00FF F924
|CFORC_PWMC EQU
38
00FF F925
|PWMC
EQU
39
00FF F926
|PWMA_B
EQU
40
00FF F928
|PWMCNT
EQU
41
00FF F92A
|PWMBUF_A_B EQU
42
00FF F92C
|PRESCL
EQU
43
|
44
|
45
|
46
|*************** DEFAULT EQUATES *********************
47
|
48
|*
These equates are for setup of the basic operation of the
49
|*
331 such as interrupt addresses and enabling certain interrupts.
50
|*
51
0000 0088
|GMCR_ARB
EQU
$0088
52
0000 0540
|GICR_D
EQU
$0540
53
0000 0100
|VEC_BASE
EQU
$0100
54
0000 0004
|V_ADDR_IC1 EQU
$01*04
55
0000 0010
|V_ADDR_OC1 EQU
$04*04
56
0000 0024
|V_ADDR_TOF EQU
$09*04
57
0000 0080
|V_ADDR_TRP EQU
32*04
58
|*
59
|
60
0000 0006
|TMSK_ID
EQU
$0006
61
0000 0980
|TMSK_IE
EQU
$0980
$FFF900
BASE ADDRESS OF GPT ON THE MC68331
GPT MCR REGISTER ADDRESS
INTERRUPT CONTROL REGISTER
PORT DATA DIRECTION REG/PORT DATA REG
PORT DATA REG IF ADDR BYTE BOUNDARY
OUTPUT CAPTURE MASK AND DATA ACTION REG
TIMER COUNTER REGISTER
PULSE ACCUM CONTROL AND COUNTER REG
TIMER INPUT CAPTURE 1 REGISTER
TIMER INPUT CAPTURE 2 REGISTER
TIMER INPUT CAPTURE 3 REGISTER
TIMER OUTPUT COMPARE 1 REGISTER
TIMER OUTPUT COMPARE 2 REGISTER
TIMER OUTPUT COMPARE 3 REGISTER
TIMER OUTPUT COMPARE 4 REGISTER
TIMER IC 4 OC 5 REG
TIMER CONTROL REGISTER 1 AND 2
TIMER INTERRUPT MASK REGISTER 1 AND 2
TIMER INTERRUPT FLAG REGISTER 1 AND 2
BYTE ADDRESS OF TFLG2
COMPARE FORCE AND PWM CONTROL REGISTER
JUST THE PWMC REGISTER
PWM REGISTER A AND B
PWM COUNT REGISTER
PWM BUFFER REGISTER A AND B (READ ONLY)
GPT PRESCALER (LOWER 9 BITS)
BASE+$04
BASE+$06
BASE+$07
BASE+$08
BASE+$0A
BASE+$0C
BASE+$0E
BASE+$10
BASE+$12
BASE+$14
BASE+$16
BASE+$18
BASE+$1A
BASE+$1C
BASE+$1E
BASE+$20
BASE+$22
BASE+$23
BASE+$24
BASE+$25
BASE+$26
BASE+$28
BASE+$2A
BASE+$2C
GPT SUPER MODE, IARB = 8 ARBITRATION
GPT PAB=0, IR=5, IVBA=$4X(VECTOR 64 DEC)
VECTOR TABLE OFFSET
IC1 VECTOR ADDRESS OFFSET
0C1 VECTOR ADDRESS OFFSET
TOF VECTOR ADDRESS OFFSET
TRAP #0 (VECTOR #32)VECTOR
ADDRESS OFFSET
DISABLE INT, SET TCNT PRESCALER TO /256
OC1,TOI AND IC1 INTERRUPTS
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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