參數(shù)資料
型號: GPTRM
英文描述: General-Purpose Timer Reference Manual
中文描述: 通用定時器參考手冊
文件頁數(shù): 23/90頁
文件大?。?/td> 647K
代理商: GPTRM
GPT
REFERENCE MANUAL
COMPARE/CAPTURE UNIT
MOTOROLA
3-1
SECTION 3 COMPARE/CAPTURE UNIT
The compare/capture unit is one of the major submodules of the GPT. It contains the
timer counter (TCNT), the input capture (IC) functions, and the output compare (OC)
functions. Refer to
Figure 3-1
.
3.1 Timer Counter
The timer counter (TCNT) is the key timing component in the compare/capture unit.
The timer counter is a 16-bit free-running counter that starts counting after the proces-
sor comes out of reset. The counter cannot be stopped during normal operation. Refer
to
SECTION 9 SPECIAL MODES
on how to stop the counter. After reset, the GPT is
configured to use the system clock divided by four as the input to the counter. The
prescaler divides the system clock and provides selectable input frequencies. User
software can configure the system to use one of seven outputs from the prescaler or
an external clock through the PCLK input pin. Refer to
SECTION 5 PRESCALER
for
more details on prescaler operation.
The counter appears as a register in the GPT and can be read any time with user soft-
ware without affecting its value. Because the GPT is interfaced to the IMB and the IMB
supports a 16-bit bus, a word read gives a coherent value. If coherency is not needed,
byte accesses can be made. The counter is set to $0000 on reset and is a read-only
register. There are two exceptions: test mode and freeze mode. Any value can be writ-
ten to the timer counter while in these modes. Refer to
9.1 Test Mode
and
9.3 Freeze
Mode
for information on test and freeze mode operation.
When the counter rolls over from $FFFF to $0000 the timer overflow bit is set in timer
interrupt flag register 2 (TFLG2). An interrupt can be enabled by setting the corre-
sponding interrupt enable bit (TOI) in the timer interrupt mask register 2 (TMSK2). Re-
fer to
7.1.2.1 Timer Interrupt Flag Registers 1–2 (TFLG1/TFLG2)
and
7.1.3.1 Timer
Interrupt Mask Registers 1–2 (TMSK1/TMSK2)
for more information on these regis-
ters; refer to
7.1 Interrupts
for information on interrupt operation.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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