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| 型號(hào)： | GPTRM |
| 英文描述： | General-Purpose Timer Reference Manual |
| 中文描述： | 通用定時(shí)器參考手冊(cè) |
| 文件頁數(shù)： | 18/90頁 |
| 文件大?。?/td> | 647K |
| 代理商： | GPTRM |
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MOTOROLA
1-6
FUNCTIONAL OVERVIEW
GPT
REFERENCE MANUAL
at the pulse accumulator. When the input is negated, the counter is stopped. Two flags
are generated: one to indicate the occurrence of an event, and the other to indicate
counter overflow. Either of these flags, when enabled, can cause the processor to be
interrupted. Refer to
Figure 1-4
.
Figure 1-4 Pulse Accumulator Simplified Block Diagram
The pulse accumulator can be used to count the number of items going by on a con-
veyor belt or the number of teeth that have gone by on a crankshaft timing gear. As
each item or tooth is detected, the counter is incremented (event counting mode). The
counter therefore contains the number of items (teeth). The flag indicates the occur-
rence of an event (an item or tooth went by). If interrupts are enabled, an interrupt is
generated. Software can read the counter at this time. Because only 255 events can
be counted before the counter overflows, the overflow flag can be used to extend the
counter range beyond eight bits.
The gated mode of operation can be used to measure the pulse width or period of an
input signal. When the input to the pulse accumulator is active, the counter begins
counting the input clock. When the signal is negated it stops counting. If the counter is
set to zero before the pulse starts, the count value multiplied by the clock period gives
the width of the input pulse to the nearest clock period. This could be used to deter-
mine how long a stimulus is present.
1.5 Pulse-Width Modulation (PWM) Concepts
A pulse-width modulated waveform is created when the high to low time ratio of a pe-
riodic rectangular signal can be varied. If the waveform can be incrementally changed
by 1/256 of its period, it has eight bits of resolution. Refer to
Figure 1-5
.
As shown in the pulse-width modulation simplified block diagram (
are two comparators per PWM function: the zero detector and the 8-bit comparator.
The PWM unit has a 16-bit counter. Each PWM function can use 8 bits; each can use
either valid set of eight bits. Every time the 8-bit counter overflows from $FF to $00,
the zero detector sets the output latch. The zero detector is used as the reference to
start the high time. As the counter is incremented, the counter value is compared with
the contents of the 8-bit register. When a match occurs the latch is reset. By changing
the value in the 8-bit register, the duty cycle is continuously variable in n/256 incre-
ments.
Figure 1-6
), there
8-BIT COUNTER
EVENT
CLOCK
GATED TIME ACCUMULATION MODE
8-BIT COUNTER
EVENT COUNTING MODE
EVENT
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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