參數(shù)資料
型號： GPTRM
英文描述： General-Purpose Timer Reference Manual
中文描述： 通用定時器參考手冊
文件頁數(shù)： 39/90頁
文件大?。?/td> 647K
代理商： GPTRM
GPT
REFERENCE MANUAL
PRESCALER
MOTOROLA
5-3
Refer to
SECTION 9 SPECIAL MODES
for information on how to stop the prescaler.
The 9-bit prescaler may be read at any time. In test or freeze mode the prescaler can
be written. Word accesses must be used to ensure coherency. If coherency is not
needed byte accesses can be used. The value of the prescaler will be in bits 8:0;
whereas, bits 15:9 are unimplemented and will be read as zeros.
NOTE
Changing the value of the prescaler while it is running may cause an
extra count if the prescaler tap bit selected is at a logic level zero, and
the new value written is a logic level one.
Two bits, STOPP and INCP in the GPT module configuration register (GMCR), can be
used to more directly control the prescaler, i.e., for testing purposes. When set the
STOPP bit stops the prescaler from counting. The INCP bit increments the prescaler
by one count if it is stopped. This bit is self negating. There should be at least one bus
cycle between writing the prescaler control bits and setting the INCP bit while single-
stepping (while the STOPP bit is set) to guarantee proper operation of the single-step-
ping feature. Writing this sequence on successive cycles may result in unpredictable
behavior. Refer to
SECTION 9 SPECIAL MODES
.
Another feature of the GPT is the capability to output the selected prescaler outputs
(including the PCLK pin) from the two multiplexers to external pins. The CPROUT bit
in the TMSK2 register configures the OC1 pin to output the TCNT clock from the timer
mux and the PPROUT bit in the PWMC register configures the PWMA pin to output
the PWM clock from the PWM mux. These two bits can be written at any time. The
clock signals on OC1 and PWMA do not have a 50% duty cycle. They have the period
of the selected clock, but are high for only one system clock time.
The prescaler also supplies three clock signals to the pulse accumulator clock select
mux. These are the system clock divided by 512, the external clock signal from the
PCLK pin, and the compare/capture clock signal.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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