參數(shù)資料
型號(hào)： GPTRM
英文描述： General-Purpose Timer Reference Manual
中文描述： 通用定時(shí)器參考手冊
文件頁數(shù)： 55/90頁
文件大?。?/td> 647K
代理商： GPTRM
GPT
REFERENCE MANUAL
SPECIAL MODES
MOTOROLA
9-1
SECTION 9 SPECIAL MODES
The GPT can enter a number of special modes in addition to its normal operational
mode. These modes are test mode (selected by a bit in the SIM module configuration
register (MCR), stop mode, freeze mode and single step mode. These different modes
are selected by bits in the MCR. One other mode, supervisor mode, allows system
software to limit access to certain registers in the GPT.
9.1 Test Mode
The test mode is intended for factory production testing of the GPT and other modules
within the specific MCU on which the GPT is incorporated. The description of the test
mode is for informational purposes only and is not intended to provide operational in-
formation. Applications should avoid using test mode.
Test mode is entered by a combination hardware and software method. A register bit
(MCR of SIM) must be set while an external pin (TSTME) is asserted.
Test mode on the GPT is only used to allow write access to registers and bits that oth-
erwise are read-only. Because the timing functions are simple, no other special test
logic is included in this module. However, the test register location is reserved by Mo-
torola for future use. Because all of the registers are accessible in various operational
modes, the prescaler, counters, and control registers can be read and written by diag-
nostic software. Also, the outputs of the prescaler muxes can be driven out on external
pins. With these simple features, the GPT can be easily tested. For more information
on test mode refer to the test submodule section in the appropriate MCU manual.
9.2 Stop Mode
In STOP mode the system clock is stopped in most of the module and will remain
stopped until the STOP bit is negated by the CPU or by a reset. All counters and pres-
calers within the timer will stop counting while the STOP bit is asserted. Only the mod-
ule configuration register (MCR) and the interrupt configuration register (ICR) should
be accessed while in the stop mode. Accesses to other GPT registers may result in
unpredictable behavior. The STOP bit should be cleared independently of the other
control bits in this register to guarantee proper operation. Changing the state of other
bits while changing the state of the STOP bit may result in unpredictable behavior. For
example, clearing the STOP bit while setting the STOPP bit may result in incrementing
the prescaler.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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