參數(shù)資料
型號(hào)： GPTRM
英文描述： General-Purpose Timer Reference Manual
中文描述： 通用定時(shí)器參考手冊(cè)
文件頁(yè)數(shù)： 47/90頁(yè)
文件大?。?/td> 647K
代理商： GPTRM
GPT
REFERENCE MANUAL
INTERRUPTS
MOTOROLA
7-1
SECTION 7 INTERRUPTS
7.1 Interrupts
The GPT is capable of generating one of seven interrupt priority levels on the inter-
module bus (IMB). The GPT contains control registers which set the interrupt priority
level and the arbitration priority of the module, enable the interrupts of the 11 interrupt
sources and adjust their priority internally.
The interrupt priority level of the GPT can be one of eight levels 7–0. This level is se-
lected by the interrupt request level (IRL) bits in the interrupt configuration register
(ICR). A level 7 is the highest priority and a level 0 disables interrupts. (Refer to
Figure
7-3
for the location of these bits in the ICR.
When an interrupt is requested and is at a higher level than the current interrupt level
set by the interrupt mask in the CPU status register, the CPU initiates an interrupt ac-
knowledge (IACK) cycle. The module will decode the IACK cycle and compare the
CPU recognized level to the level that the module is currently requesting. Refer to the
appropriate CPU manual for more information on the interrupt mask. If a match occurs,
arbitration with other modules begins.
Interrupting modules present their arbitration ID on the IMB and the module with the
highest ID wins. If the GPT wins the arbitration, it generates a uniquely encoded inter-
rupt vector that indicates which timer channel is requesting service. The encoding
scheme is such that the high nibble of the interrupt vector (called the interrupt vector
base address;) comes from a 4-bit field in the interrupt configuration register; (ICR).
The encoded value of the low-order nibble, the interrupt source number, source num-
ber, indicates which of the 11 interrupt sources of the GPT is requesting service.
Fig-
ure 7-2
shows a block diagram of the interrupt hardware.
The arbitration ID for the GPT module is selected by the IARB bits in the GPT module
configuration register (MCR) (
Figure 7-1
). The IMB is designed to arbitrate between a
maximum of 16 modules, so the IARB field of the MCR can have a value from 0
through 15. A module with an IARB of 15 always wins the arbitration when two or more
modules with the same interrupt level contend for the interrupt request. Each module
should have a unique Arbitration ID.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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