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| 型號： | GPTRM |
| 英文描述： | General-Purpose Timer Reference Manual |
| 中文描述： | 通用定時器參考手冊 |
| 文件頁數(shù)： | 50/90頁 |
| 文件大?。?/td> | 647K |
| 代理商： | GPTRM |
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MOTOROLA
7-4
INTERRUPTS
GPT
REFERENCE MANUAL
IRL — Interrupt Request Level
These bits specify the priority level of the GPT module's interrupts. The GPT can have
any of eight priority levels. Level 7 is the highest priority and is nonmaskable. Level
zero disables interrupts. The interrupt request level specifies the priority level present-
ed to the CPU. The interrupt request level is initialized to zero during reset.
All GPT internal interrupts are prioritized as shown in
Table 7-1
. The interrupt with the
highest priority generates the interrupt level to the IMB specified by this field.
VBA — Interrupt Vector Base Address
This field specifies the most significant nibble of all the vector numbers that can be
generated by the different interrupt sources of the GPT module. This value concate-
nated with the vector address shown in
Table 7-1
is the module interrupt vector. The
“X” in the table represents the VBA.
7.1.2 Interrupt Status Flags
When an event occurs in the GPT (such as a timer overflow, an input capture, or any
event that could generate an interrupt), that event sets a status flag in the timer inter-
rupt flag registers (TFLG1/TFLG2). User software can read the status registers to de-
tect an event. If an event occurred, the polling routine can transfer control to a software
routine that services that event.
If interrupts are enabled for that event, the CPU enters an interrupt service routine. Us-
ing interrupts does not require continuously polling the status flags to detect the occur-
rence of an event.
The interrupt status flags must be cleared in a particular sequence. A read operation
must first be executed on the asserted status flag and then a write of the negated state
must be executed. With the GPT, all of the status flags are at a logic level one when
asserted; therefore, a logic level zero must be written to clear the flag. If a new event
occurs between the CPU reading the status and clearing it, the flag will not be cleared,
indicating the occurrence of a new event.
The GPT, and never the CPU, asserts the interrupt status flags. The CPU can only
clear them. The term “clear” means to negate or, in the present case, set the flag to a
logic level zero.
Figure 7-4
shows the timer interrupt flag registers.
7.1.2.1 Timer Interrupt Flag Registers 1–2 (TFLG1/TFLG2)
The timer interrupt flag register indicates when an event occurs in the GPT and is di-
vided into two 8-bit registers: TFLG1 and TFLG2. The registers can be addressed as
one 16-bit register or as individual 8-bit registers. The registers initialize to zero at re-
set.
This register along with the timer interrupt mask registers (TMSK1/TMSK2) allow the
GPT to operate in a polled or interrupt-driven system. For each bit in TFLGx there is a
corresponding bit in the TMSKx register in the same bit position. If the mask bit is set
and an associated event occurs, a hardware interrupt request is generated. Refer to
7.1.3 Enabling Interrupts
for more detail.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
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