參數(shù)資料
型號(hào)： FUSB2805MLX
廠商： Fairchild Semiconductor
文件頁(yè)數(shù)： 8/49頁(yè)
文件大?。?/td> 0K
描述： TXRX USB2.0 HS OTG ULPI 32MLP
標(biāo)準(zhǔn)包裝： 1
系列： *
其它名稱(chēng)： FUSB2805MLXFSDKR
2008 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FUSB2805 Rev. 1.0.3
16
F
USB2
8
0
5
—
USB2
.0
High
-S
pee
d
OTG
Tra
nsc
e
iv
e
rw
ith
UL
P
I
Inter
fac
e
USB Packet Transmit and Receive
When transmitting and receiving USB packets, there
are limits set on the link and PHY processing time to
ensure that USB inter-packet delays are also met.
These times are determined by the USB event and the
packet format (i.e. transmit with PID or NOPID, transmit
error, receive error, etc.).
Link sends
TXCMD
CLOCK
D0-D7
STP
DIR
NXT
DATA
RXCMD
DATA
TXCMD
turn
around
turn
around
FUSB2500
accepts
TXCMD
Link sends
next data.
FUSB2500
accepts.
Link signals
end of data
ULPI bus is
idle
FUSB2500
asserts DIR,
causing
turnaround cycle
FUSB2500
sends
RXCMD
(NXT low)
FUSB2500
sends USB
data
(NXT high)
FUSB2500
de-asserts DIR,
causing
turnaround cycle
Figure 10. Example ULPI Packet Transmit and Receive
Note:
10. Please refer to ULPI specifications section 3.8.2 for further detail on USB packet operations and functionality.
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