參數(shù)資料
型號(hào)： FUSB2805MLX
廠商： Fairchild Semiconductor
文件頁(yè)數(shù)： 6/49頁(yè)
文件大?。?/td> 0K
描述： TXRX USB2.0 HS OTG ULPI 32MLP
標(biāo)準(zhǔn)包裝： 1
系列： *
其它名稱： FUSB2805MLXFSDKR
2008 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FUSB2805 Rev. 1.0.3
14
F
USB2
8
0
5
—
USB2
.0
High
-S
pee
d
OTG
Tra
nsc
e
iv
e
rw
ith
UL
P
I
Inter
fac
e
Link sends
TXCMD
CLOCK
D0-D7
STP
DIR
NXT
DATA
RXCMD
DATA
TXCMD
Turn
around
Turn
around
FUSB2805
accepts
TXCMD
Link sends
next data.
FUSB2805
accepts
Link signals
end of data
ULPI bus
is idle
FUSB2805
asserts DIR,
causing
turnaround cycle
FUSB2805
sends
RXCMD
(NXT low)
FUSB2805
sends USB
data
(NXT high)
FUSB2805
de-asserts DIR,
causing
turnaround cycle
Figure 8. ULPI Generic Data Transmit Followed by Data Receive
On power-up, the FUSB2805 performs an internal
power-on reset and asserts DIR to indicate to the link
that the ULPI bus cannot be used. When the internal
PLL is stable, the FUSB2805 de-asserts DIR. The
power-up time depends on the VCC supply rise time and
the PLL startup time (tstartPLL).
Whenever DIR is asserted, the FUSB2805 drives the
NXT pin LOW and must drive the data bus (D0-D7) with
RXCMD values. When DIR is de-asserted, the link must
drive the data bus (D0-D7) to the default LOW. Before
beginning USB packets, the FUSB2805 is reset by the
link setting the RESET bit in the function control
register. After the RESET bit is set, the FUSB2805
asserts DIR until the internal reset completes. The
FUSB2805 automatically de-asserts DIR and clears the
RESET bit when the reset has completed. After every
reset, an RX CMD is sent to the link to update USB
status information. After this sequence, the ULPI bus is
ready for use and the link can start USB operations.
If Chip_Select_N is de-asserted, the FUSB2805 is
retained in power-down mode, where all ULPI interface
pins are three-state, internal regulators are shut down,
and power consumption is reduced even further than in
low-power mode.
If low-power mode is entered due to no VIO, the
recommended power-up sequence for the link is:
1.
Connect VCC and VIO supplies.
2.
Chip_Select_N goes HIGH to LOW to enable the
FUSB2805.
3.
Link waits for at least tPWRUP, ignoring all ULPI pins
status.
4.
The link may start to detect DIR status level; if the
DIR is detected LOW, the link may send a reset
command.
5.
The ULPI interface is ready for use.
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