參數(shù)資料
型號(hào)： FUSB2805MLX
廠商： Fairchild Semiconductor
文件頁(yè)數(shù)： 47/49頁(yè)
文件大小： 0K
描述： TXRX USB2.0 HS OTG ULPI 32MLP
標(biāo)準(zhǔn)包裝： 1
系列： *
其它名稱： FUSB2805MLXFSDKR
2008 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FUSB2805 Rev. 1.0.3
7
F
USB2
8
0
5
—
USB2
.0
High
-S
pee
d
OTG
Tra
nsc
e
iv
e
rw
ith
UL
P
I
Inter
fac
e
Detailed Description of Pins
D0 to D7
D0 to D7 are bi-directional ULPI data bus pins. The
USB link controller must drive D0-D7 LOW when the
ULPI bus is idle (DIR is LOW). When the link has data
to transmit to the FUSB2805, it drives a non-zero value.
The data bus can be re-configured to carry different
data types. There are four modes of the data bus:
Synchronous mode: default is SDR mode
(3), with
the 8-bit data bytes being synchronous to the rising
edge of CLOCK.
Low-power mode: carries asynchronous line state
and
VBUS information.
3-pin serial mode: carries asynchronous 3-pin
FS/LS serial signaling.
6-pin serial mode: carries asynchronous 6-pin
FS/LS serial signaling.
Data
pins
can
also
be
three-stated
by
driving
chip_select_N HIGH.
Note:
3.
DDR is not supported by the FUSB2805.
VIO
VIO is the input power pin that sets the I/O voltage level.
VIO powers the on-chip pads of the following pins:
CLOCK
DIR
STP
NXT
D0-D7
RESET_N
CFG1
RREF
Resistor reference analog I/O pin. A 12 k
1% resistor
is required.
DP and DM
When in USB mode, the DP pin functions as USB data
plus line; the DM pin functions as USB data minus line.
The DP and DM pins should be connected to the D+
and D- pins of the USB receptacle.
FAULT
This input pin is used by an external SMPS or power
management IC to signal an over-current or over-
voltage fault condition. This is applicable in OTG host
where PSW is used to control driving VBUS or signaling
for
higher
charging
currents
to
an
OTG
SMPS
management IC, as shown in Figure 5.
ID
For OTG implementation, the ID (identification) pin is
connected to the ID pin of the mini-USB (or micro-USB)
receptacle. As defined in the OTG specification, the ID
pin dictates the initial role of the link controller. If ID is
detected as HIGH, the link controller must assume the
role of peripheral. If ID is detected as LOW, the link
controller must assume the host role. Roles can be
swapped later using Host Negotiation Protocol (HNP).
The FUSB2805 provides an internal pull-up resistor to
sense the value of the ID pin. The pull-up resistor, with
a value of 50 k
, must first be enabled by setting the
ID_PULLUP register bit to 1b. If the value on ID has
changed, the FUSB2805 sends an RX CMD or interrupt
to the link controller by time tID. If the link controller
does not receive any RX CMD or interrupt by tID, then
the ID value has not changed.
To avoid a floating ID pin, a 400 k
resistor pull-up is
switched in when ID_PULLUP register bit is set to 0b.
5V
USB Trans
PSW
VBUS
Digital over-current protection scheme
with external power switch
VBUS
OTG Host
Supply
Source
Switch with
External
Over-
Current
Detector
FAULT
100k
Figure 5. Digital Over-Current Detection Scheme
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