參數(shù)資料
型號(hào)： FUSB2805MLX
廠商： Fairchild Semiconductor
文件頁(yè)數(shù)： 32/49頁(yè)
文件大?。?/td> 0K
描述： TXRX USB2.0 HS OTG ULPI 32MLP
標(biāo)準(zhǔn)包裝： 1
系列： *
其它名稱(chēng)： FUSB2805MLXFSDKR
2008 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FUSB2805 Rev. 1.0.3
38
F
USB2
8
0
5
—
USB2
.0
High
-S
pee
d
OTG
Tra
nsc
e
iv
e
rw
ith
UL
P
I
Inter
fac
e
USB Interrupt Enable (Rising) Register
– INTR_EN_R_CTRL (0Dh-0Fh Read, 0Dh Write,
0Eh Set, 0Fh Clear)
These
register
bits
control
the
interrupt
event
notification settings of the FUSB2805 for LOW-to-HIGH
signal changes. By default, all transitions are enabled.
Interrupt circuitry can be powered down in any mode
when both rising and falling edge enables are disabled.
To ensure interrupts are detectable when CLOCK is
powered down, the link should enable both rising and
falling edges.
Table 20. USB Interrupt Enable (Rising) Register
Field Name
Bits
Access Reset
Description
HostDisconnect Rise
0
rd/wr/s/c
1b
Generates an interrupt event notification when HostDisconnect
changes from LOW to HIGH. Applicable only in host mode
(DpPulldown and DmPulldown both set to 1b).
VBUSValid Rise
1
rd/wr/s/c
1b
Generates an interrupt event notification when VBUSValid changes
from LOW to HIGH.
SessValid Rise
2
rd/wr/s/c
1b
Generates an interrupt event notification when SessValid changes
from LOW to HIGH. SessValid is the same as UTMI+ AValid.
SessEnd Rise
3
rd/wr/s/c
1b
Generates an interrupt event notification when SessEnd changes
from LOW to HIGH.
IDGnd Rise
4
rd/wr/s/c
1b
Generates an interrupt event notification when IDGnd changes
from LOW to HIGH. IDGnd is valid 50 ms after IDPullup is set to
1b; otherwise, IDGnd is undefined and should be ignored.
RESERVED
7:5
rd/wr/s/c
0b
Reserved
USB Interrupt Enable (Falling) Register
– INTR_EN_F_CTRL (10h-12h Read, 10h Write,
11h Set, 12h Clear)
These
register
bits
control
the
interrupt
event
notification settings of the FUSB2805 for HIGH-to-LOW
signal changes. By default, all transitions are enabled.
Interrupt circuitry can be powered down in any mode
when both rising and falling edge enables are disabled.
To ensure interrupts are detectable when CLOCK is
powered down, the link should enable both rising and
falling edges.
Note:
24. RxActive and RxError must always be
communicated immediately, these events are not
included in this register.
Table 21. USB Interrupt Enable (Falling) Register
Field Name
Bits
Access
Reset
Description
HostDisconnect Fall
0
rd/wr/s/c
1b
Generates an interrupt event notification when HostDisconnect
changes from HIGH to LOW. Applicable only in host mode
(DpPulldown and DmPulldown both set to 1b).
VBUSValid Fall
1
rd/wr/s/c
1b
Generates an interrupt event notification when VBUSValid changes
from HIGH to LOW.
SessValid Fall
2
rd/wr/s/c
1b
Generates an interrupt event notification when SessValid changes
from HIGH to LOW. SessValid is the same as UTMI+ AValid.
SessEnd Fall
3
rd/wr/s/c
1b
Generates an interrupt event notification when SessEnd changes
from HIGH to LOW.
IDGnd Fall
4
rd/wr/s/c
1b
Generates an interrupt event notification when IDGnd changes
from HIGH to LOW. IDGnd is valid 50ms after IDPullup is set to
1b; otherwise, IDGnd is undefined and should be ignored.
RESERVED
7:5
rd/wr/s/c
0b
Reserved
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