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參數(shù)資料
| 型號： | FUSB2805MLX |
| 廠商： | Fairchild Semiconductor |
| 文件頁數(shù)： | 17/49頁 |
| 文件大小： | 0K |
| 描述： | TXRX USB2.0 HS OTG ULPI 32MLP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
| 其它名稱： | FUSB2805MLXFSDKR |
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2008 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FUSB2805 Rev. 1.0.3
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Register Read and Write Operations
The link can read or write register bytes, and set or
clear register bits as needed, using the TXCMD byte.
The FUSB2805 supports immediate and extended
addressing register operations, with the extended
register addressing being optional for the link. If the
FUSB2805 asserts DIR during an operation, the register
operation is aborted. When a register operation is
aborted, the link must retry until successful.
Immediate Register Read and Write
Immediate address registers are accessed by first
sending the TXCMD byte as either a RegRead or
RegWrite command with the required register address.
For RegRead, the link sends its read command request
and waits for NXT to assert. In the cycle after NXT
asserts, the FUSB2805 asserts DIR to gain control of
the bus. In the cycle after DIR asserts, the FUSB2805
must return the register read data. The FUSB2805 does
not assert NXT when DIR is asserted during the register
read operation, including during the period that the
register read data is being returned, to ensure that a
USB receive event always overrides the register read
during any cycle (see section 3.8.3.2 of ULPI Rev. 1.1
specification). If the FUSB2805 aborts the RegRead by
asserting DIR early, the link must retry the RegRead
when the bus is idle.
For RegWrite, the link sends its write command request
and waits for NXT to assert. In the cycle after NXT
asserts, the link sends the register write data and waits
for NXT to assert again. When NXT asserts the second
time, the link asserts STP in the following cycle to
complete the operation. The FUSB2805 must detect
STP assertion before it accepts another transmit
command. If the FUSB2805 aborts the RegWrite by
asserting, DIR the link must retry the RegWrite when
the link is idle.
For back-to-back read/write and USB receive signaling,
refer to ULPI specifications, section 3.8.3.3 for details
and timing waveforms.
Extended Register Read and Write
Extended addressing read (EXTR) and write (EXTW)
means that the address is available in the next clock
cycle. Accessing immediate address 2Fh indicates an
access to the extended register set.
For an EXTR (extended register read), the link sends a
register-read command with the address set to 2Fh and
waits for NXT to assert. In the cycle after NXT asserts,
the link sends the extended register address and waits
for NXT to assert again. When NXT asserts the second
time, the FUSB2805 asserts DIR to gain control of the
bus. In the cycle after DIR asserts, the FUSB2805 must
return the register read data. The FUSB2805 does not
assert NXT when DIR is asserted during the register
read operation, including during the period that the
register read data is being returned, to ensure that a
USB receive event always overrides the register read
during any cycle (see section 3.8.3.5 of ULPI Rev. 1.1
specification). If the FUSB2805 aborts the RegRead by
asserting DIR early, the link must retry the RegRead
when the bus is idle.
For an EXTW (extended register write), the link sends a
register write command with the address set to 2Fh and
waits for NXT to assert. In the cycle after NXT asserts,
the link sends the extended register address and waits
for NXT to assert again. When NXT asserts the second
time, the link sends the register write data and waits for
NXT to assert again. When NXT asserts the third time,
the link asserts STP in the following cycle to complete
the operation. If the FUSB2805 aborts the RegWrite by
asserting DIR, the link must retry the RegWrite when
the bus is idle.
For back-to-back extended read and USB receive
signaling, refer to ULPI specifications section 3.8.3.5 for
details and timing waveforms.
Please refer to ULPI specification, section 3.8.3 for
details on register read and write operations and
functionality.
Aborting ULPI Transfers
There are two ways to abort ULPI transfers:
Link aborted by the FUSB2805
FUSB2805 aborted by the link.
Link Aborted by the FUSB2805
When the link is transferring data, the FUSB2805 can
abort the link by asserting DIR.
FUSB2805 Aborted by the Link
When FUSB2805 has DIR asserted (in synchronous
mode), the link can abort by asserting STP. There are
very specific criteria to meet in the timing diagram to
guarantee the link transaction, which is related to the
cycle in which STP is asserted by the link to request
aborting the FUSB2805 (see section 3.3.4.2 of the ULPI
Rev. 1.1 specification for timing details). While this
feature can be used at any time, it is provided to
terminate a “babbling” port by disabling the FUSB2805.
The FUSB2805 cannot guarantee the validity of USB
data during the current packet and the next packet if the
link asserts STP during a USB receive packet.
Please refer to ULPI specification, section 3.8.4 for
details on aborting ULPI transfers.
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