參數(shù)資料
型號(hào): FUSB2805MLX
廠商: Fairchild Semiconductor
文件頁數(shù): 49/49頁
文件大?。?/td> 0K
描述: TXRX USB2.0 HS OTG ULPI 32MLP
標(biāo)準(zhǔn)包裝: 1
系列: *
其它名稱: FUSB2805MLXFSDKR
2008 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FUSB2805 Rev. 1.0.3
9
F
USB2
8
0
5
USB2
.0
High
-S
pee
d
OTG
Tra
nsc
e
iv
e
rw
ith
UL
P
I
Inter
fac
e
Modes of Operation
ULPI Modes
The ULPI bus can be programmed to operate in four
different modes and a power-down mode. Each mode
re-configures the signals on the data bus. Setting more
than one mode leads to undefined behavior.
Synchronous Mode
This is the default mode. On power-up and when CLOCK
is stable, the FUSB2805 enters synchronous mode.
In
synchronous
mode,
the
link
controller
must
synchronize all ULPI signals to CLOCK, meeting the
setup
and
hold
times
defined
in
the
Dynamic
Characteristics tables.
This mode is used by the link controller to perform the
following tasks:
Detect high-speed handshake (chirp)
Transmit and receive USB packets
Read and write to registers
Receive USB status updates (RX CMDs) from
FUSB2805
Please refer to section 3.8 of the ULP Rev. 1.1
specification for further details.
Low-Power Mode
When the USB is idle, the link controller can place the
FUSB2805 into low-power mode (also known as
“suspend” mode). To enter low-power mode, the link
controller clears the SUSPENDM bit in the function
control (FUNC_CTRL) register to 0b.
During low-power mode, the FUSB2805 provides line
state and interrupt information on the data bus for the
link controller to monitor basic USB states and draws
less than 200 A from the VCC supply.
In addition, during low-power mode, the clock on CLKIN
may be stopped; but it must be restarted before
asserting STP to exit low-power mode.
Once in low-power mode, the FUSB2805 must remain
in low-power mode for a minimum of 120 clock cycles
(or 2 s). After the 2 s delay, low-power mode may be
exited by asserting the STP signal. The FUSB2805 then
issues an RXCMD to the link if a change was detected
in any interrupt source and the change still exists. An
RXCMD may not be sent if the interrupt condition is
removed before exiting.
In low-power mode, the data bus assignments are
changed to those described in Table 1.
Table 1.
Signal Mapping on ULPI Bus During Low-Power Mode
Signal
Maps To Direction
Description
LINESTATE0
D0
Out
Combinatorial LINESTATE0 directly driven by the analog receiver
LINESTATE1
D1
Out
Combinatorial LINESTATE1 directly driven by the analog receiver
RESERVED
D2
Out
Reserved; the FUSB2805 drives this pin LOW
INT
D3
Out
Active-HIGH interrupt signal; asserted and latched whenever any
unmasked interrupt occurs
RESERVED
D[7:4]
Out
Reserved; the FUSB2805 drives these pins LOW
Entering Low-Power Mode
The link sets SuspendM=0b (in Function Control
Register) to place the FUSB2805 into low-power
mode. The CLOCK may be stopped a minimum of
five (5) cycles after the FUSB2805 accepts the
register write data as described in Figure 6. When
entering low-power mode, the FUSB2805 asserts DIR
and holds NXT LOW. There is one cycle of data bus
turnaround provided after the assertion of DIR, during
which the value of D[7:0] is not valid. Upon
completion of the turnaround cycle the FUSB2805
begins driving the signals as described in Table 1.
相關(guān)PDF資料
PDF描述
FXLA2203UMX TRANSLATOR LEVEL DUAL 24UMLP
GAL16V8D-15LJN SPLD 62.5MHZ EECMOS 20 PLCC
GAL18V10B-20LP IC GAL 10OUT MACROCELL 7.5NS 20
GAL22V10D-25LJ IC SPLD 3.3V 28-PLCC
GH65C11-C-PD OPTO ENCODER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
FUSCA REF BOARD 制造商:TDK 功能描述:REFERENCE BOARD FUSCA 2.4GHZ
FUSCAREFBOARD 制造商:Antenova 功能描述:Reference Board Fusca 2.4GHz
FUSE 功能描述:保險(xiǎn)絲 Fuse, Fiber 20A 600V Lot Qty 5 RoHS:否 制造商:Littelfuse 產(chǎn)品:Surface Mount Fuses 電流額定值:0.5 A 電壓額定值:600 V 保險(xiǎn)絲類型:Fast Acting 保險(xiǎn)絲大小/組:Nano 尺寸:12.1 mm L x 4.5 mm W 安裝風(fēng)格: 端接類型:SMD/SMT 系列:485
FUSE 25A ATC 制造商:American Technical Ceramics Corp 功能描述: 制造商:ATC 功能描述:
FUSE KIT D 制造商:COOPER BUSSMANN 功能描述:BUSSMANN FUSE KIT