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參數(shù)資料
| 型號： | FMS988AKAC140 |
| 英文描述： | Signal Conditioner |
| 中文描述： | 信號調(diào)理 |
| 文件頁數(shù)： | 6/29頁 |
| 文件大小： | 481K |
| 代理商： | FMS988AKAC140 |
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PRODUCT SPECIFICATION
FMS9875
6
REV. 1.2.15 1/14/02
Register Definitions
PLL Control Register (01)
PHASE
7-0
0B
Sampling clock phase.
PHASE
4-0
stored in upper
register bits 7-3. PHASE sets the sampling clock phase in
11.25° increments. Default value is decimal 16.
80
PLLCTRL
CONFIG 2
0C
0D
0E
0F
PLL Control.
Configuration Register No. 2.
Clamp Control Register.
Reserved.
24
00
00
00
Bit no.
1-0
Name
SUBDIV
1-0
Type
R/W
Description
PLL Subdivide ratio.
Selects the ratio of the divider following the PLL.
00:
divide-by 1
01:
divide-by 2
10:
divide-by 4
11:
reserved
2
PLLFAZ
R/W
PLL Sub-divider Phase.
Selects the phase of the divide-by-2 output.
(Invalid for other outputs)
Reserved.
PLL divide ratio, LSBs.
PLLN + 1 = total number of pixels per horizontal line.
3
–
R/W
R/W
7-4
PLLN
3-0
Configuration Register 1 (0A)
Bit no.
0
1
Name
Type
Description
XCKSEL
R/W
External Clock Select.
Select internal clock source.
0:
Internal PLL
1:
XCK input.
External Clamp Polarity.
Select clamp polarity.
0:
Active L.
1:
Active H.
External Clamp Select.
Select clamp source.
0:
Internally generated by PLL referenced to HSIN.
1:
External CLAMP input.
Coast Polarity.
Select COAST input polarity.
0:
Active L.
1:
Active H.
HSIN Polarity.
Select horizontal sync input polarity. PLL is locked to selected
edge:
0:
Falling edge.
1:
Rising edge.
1:
1:
2
XCLAMPOL
R/W
3
XCLAMP
R/W
4
COASTPOL
R/W
5
HSPOL
R/W
6
7
—
—
R
R
Name
Address
Function
Default (hex)
PHASE
4–0
X X X
SUBDIV
1–0
X X X X
PLLN
3–0
X X X
X
X X
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