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| 型號： | FMS988AKAC140 |
| 英文描述： | Signal Conditioner |
| 中文描述： | 信號調(diào)理 |
| 文件頁數(shù)： | 25/29頁 |
| 文件大小： | 481K |
| 代理商： | FMS988AKAC140 |
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FMS9875
PRODUCT SPECIFICATION
REV. 1.2.15 1/14/02
25
Applications Information
For additional applications information see Applications
Notes available from the factory.
To minimize component count, use of the following on-chip
circuits is recommended:
1.
ADC sampling clock.
2.
Clamp.
3.
Voltage reference
Optimum PLL Configuration Register (address 0x0C)
settings for typical modes are listed in Table 7. Unless
otherwise indicated, all modes are compliant with VESA or
SMPTE specifications. For unlisted modes, values should be
adjusted to optimize performance.
By adjusting the values in the gain (GRP, GGY, GBP) and
offset (OSRO, OSGY, OSBP) registers, the input conversion
range can be matched to the incoming analog signals.
AC Coupled Digitizer
Shown in Figure 24 is an implementation of a video digitizer
with AC coupled YP
B
P
R
inputs. Horizontal sync input.
Output data is three channel 24-bit pixels with a maximum
rate of 140Ms/s. Data is clocked out on the negative edge of
DCK. HSOUT is delayed HSIN.
Control is through the serial port with 150
resistors
inserted to allow interfacing with 5V logic. If the serial bus is
operates with 3.3V levels, these resistors are unnecessary.
Figure 24. Schematic, VGA Digitizer, AC Coupled RGB
VPLL
VADC
VPLL
VDIG
REFOUT
F
R2
75
R6
3.3k
C2
C5
0.0039uF
0.039uF
C6
0.1uF
RN1
100
RN2
100
RN3
100
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
F
F
F
.0C3
.047uF
.047uF
R3
75
C1
R1
75
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
C4
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
U1
FMS9875
43
44
46
45
47
73
48
9
4
21
15
4
4
3
3
3
10
22
23
24
25
16
30
20
8
1
1
1
2
2
3
4
4
5
6
7
8
9
9
9
9
6
98
97
96
87
88
26
27
33
37
39
5
7
1
1
1
1
5
6
6
7
8
9
1
2
89
74
75
1
9
9
31
34
35
83
82
81
80
79
78
77
76
58
57
56
55
54
53
52
51
70
69
68
67
66
65
64
63
86
NC1
NC4
NC7
BPIN
YGREF
CLAMP
RPIN
G
G
G
YGIN
G
BPREF
SDA
SCL
A0
A1
RPREF
HSIN
CKINV
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
REFIN
REFOUT
PWRDN
DCK
HSOUT
VDDP
V
V
V
V
V
V
V
V
V
V
V
V
G
ACSIN
DCSOUT
NC8
V
V
V
COAST
XCK
LPF
DYG0
DYG4
DPR0
DPR3
DPR5
DPB0
DPB2
DPB4
DCK
R7
47
R8
47
R4
150
R5
150
A1
INVSCK
HSIN
Y
A0
PR
YDATA [7..0]
PBATA [7..0]
PRATA [7..0]
CLAMP
SDA
PB
DCK
DCK
SCL
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