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參數(shù)資料
| 型號： | FMS988AKAC140 |
| 英文描述： | Signal Conditioner |
| 中文描述： | 信號調(diào)理 |
| 文件頁數(shù)： | 11/29頁 |
| 文件大?。?/td> | 481K |
| 代理商： | FMS988AKAC140 |
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FMS9875
PRODUCT SPECIFICATION
REV. 1.2.15 1/14/02
11
Within the A/D converter core are the following elements:
1.
Differential track and hold.
2.
Differential analog-to-digital converter.
Setting the gain register value G
7-0
(GRP
7-0
, GGY
7-0
, GBP
7-0
),
establishes the gain D/A converter voltage which is the upper
A/D reference voltage. Increasing the gain register value
reduces the output level. Conversion range is defined by the gain
setting according to Table 5.
Table 5. Gain Calibration
A/D Converter sensitivity is:
Offset is set through the Track and Hold, which translates the
ground referenced input to a differential voltage centered
around A/D common mode bias voltage.
The 6-bit Offset D/A converter injects a current into R
LEVEL
with two components:
1.
I
BIAS
to establish the A/D common mode voltage.
I
OFFSET
to set the offset from the common mode level.
2.
Voltage offset from the common mode voltage at the invert-
ing input of the Track and Hold is:
D/A converter gain tracks A/D gain with 1 LSB of offset
corresponding to 1LSB of gain. Increasing the offset of a
video signal increases brightness of the picture. Data output
from the A/D converter is:
Impact of the offset values OSGY
5-0
, OSBP
5-0
, and OSRP
5-0
is shown in Table 6.
Table 6. Offset Calibration
Sampling Clock PHASE Adjustment
Bandwidth of TV video is typically well below the horizon-
tal sampling rate. Consequently, PHASE has little impact on
images sampled in the YP
B
P
R
format or RGB signals derived
from a video source. By contrast, PC-generated image
quality is strongly impacted by the PHASE
4-0
value. If
PHASE is not set correctly, any section of an image
consisting of vertical lines may exhibit tearing.
Figure 3 shows how an analog input, V
IN
is sampled by the
rising edge of SCK after a delay PHASE from the rising
edge of either PXCK or XCK. SCK can be delayed up to 32
steps in 11.25° increments by adjusting the register value,
PHASE
4-0
.
G
7-0
0
102
255
Conversion Range (mV)
500
700
1000
S
500
=
+
255
G
7
0
–
----------255
OS
5-0
0
31
63
Equivalent Offset (bits)
-31
d
0
32
d
V
OS
OS
5 0
–
31
–
(
)
255
---------+
G
255
255
500
=
D
7 0
–
S
V
IN
OS
5 0
–
31
–
(
)
–
=
Figure 2. A/D Converter Architecture
A/D
D
7-0
V
IN
+
Track &
Hold
-
D/A
Current
D/A
Gain
Register
Offset
Register
R
LEVEL
SCK
I
BIAS
+ I
OFFSET
V
REF
G
7-0
OS
5-0
A/D Core
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