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| 型號(hào)： | FMS988AKAC140 |
| 英文描述： | Signal Conditioner |
| 中文描述： | 信號(hào)調(diào)理 |
| 文件頁(yè)數(shù)： | 3/29頁(yè) |
| 文件大?。?/td> | 481K |
| 代理商： | FMS988AKAC140 |
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FMS9875
PRODUCT SPECIFICATION
REV. 1.2.15 1/14/02
3
Phase Locked Loop
With a horizontal sync signal connected to the HSIN input
pin, the PLL generates a high frequency internal clock sig-
nal, PXCK that is fed to the Timing and Control logic. Fre-
quency of PXCK is set by the register programmable PLL
divide ratio, PLLN.
COAST is an input that disables the PLL lock to the horizon-
tal sync input, HSIN. If HSIN is to be disregarded for a
period such as the vertical sync interval, COAST allows the
VCO frequency to be maintained. Missing horizontal sync
pulses during the vertical interval can cause tearing at the top
of a picture, if COAST is not used.
Two pixels per clock mode is set by programming the PLL
to half the pixel rate. By toggling the INVCK pin between
frames, even and odd pixels can be read on alternate frames.
Serial Interface
Registers are accessed through an I
serial port. Four serial addresses are pin selectable.
2
C/SMBus compatible
Pin Assignments
100-Lead MQFP (KG)
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
DYG (7)
DYG (6)
DYG (5)
DYG (4)
DYG (3)
DYG (2)
DYG (1)
DYG (0)
GND
VDDO
DCK
DCK
HSOUT
DCSOUT
GND
VDDO
GND
GND
GND
VDDA
PWRDNB
REFOUT
REFIN
VDDA
VDDA
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
VDDO
GND
NC
NC
NC
NC
NC
NC
GND
GND
GND
VDDP
GND
VDDP
GND
LPF
XCK
VDDP
GND
COAST
HSIN
GND
GND
VDDP
VDDP
7
7
7
7
7
7
6
6
6
6
6
6
6
6
6
6
5
5
5
5
5
5
5
5
5
N
N
N
V
G
D
D
D
D
D
D
D
D
V
G
V
G
D
D
D
D
D
D
D
D
1
2
3
4
5
6
7
8
9
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
G
A
Y
Y
V
G
V
G
B
B
V
G
V
G
R
R
V
G
V
I
C
S
S
A
A
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