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參數(shù)資料
| 型號： | FMS988AKAC140 |
| 英文描述： | Signal Conditioner |
| 中文描述： | 信號調(diào)理 |
| 文件頁數(shù)： | 12/29頁 |
| 文件大小： | 481K |
| 代理商： | FMS988AKAC140 |
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PRODUCT SPECIFICATION
FMS9875
12
REV. 1.2.15 1/14/02
Output data and clocks: DCK and DCK are delayed in tan-
dem with SCK relative to PXCK or XCK. There is a 5-5
1
/
2
clock latency between the data sample S
n
and the corre-
sponding data out DA
7-0
.
Ideally, incoming pixels (PC generated) would be trape-
zoidal with fast rise-times and the sampling edge of the A/D
clock, SCK would be positioned along the level section of
the incoming pixel waveform as shown in Figure 4. There is
a narrow zone of uncertainly where sampling during pixel
rise time would cause an error in the value of the A/D data
output, D
7-0
, which is shown as a value, 0-255.
Figure 4. Ideal Pixel Sampling
In practice, high-resolution pixels have relatively long rise-
times. As shown in Figure 5, there are narrow zones of seren-
dipity when the pixel amplitude is level. Samples are valid in
these zones.
Figure 5. Acceptable Pixel Sampling
Referring to Figure 6, when the sample clock, SCK has some
jitter, if the sampling edge occurs anywhere within the zone
of uncertainty where the pixel rise time is steep, there will be
amplitude modulation of the digitized data, D
7-0
, due to the
sampling clock jitter. To avoid corruption of the image, set-
ting the value PHASE
7-0
is critical. PHASE
4-0
should be
trimmed to position the sampling edge of SCK within the
zone of serendipity.
Figure 6. Improper Pixel Sampling
Voltage References
An on-chip voltage reference is generated from a bandgap
source. V
REFOUT
is the buffered output of this source that
can be connected to V
REFIN
to supply a voltage reference
that is common to the three converter channels.
V
REFIN
, with a nominal voltage of 1.25V, is the source of the
differential reference voltages for each A/D converter.
Reference voltages supplied to the differential inputs of the
comparators in the A/D converters are derived from V
REFIN
.
Digital Data Outputs
Input horizontal sync HSIN and outgoing data, D[7..0] are
resynchronized to the internal delayed sample clock, SCK.
Output timing relationships are defined in Figure 7. Latency of
the first pixel, N varies according to the mode:
1.
2.
Normal.
Alternate pixel sampling.
Data transitions on the falling edge of the DCK clock. Pixel
data should be sampled on the rising edge of the DCK clock.
Levels are 3.3 volt CMOS. PWRDN = L sets the outputs
high-impedance. PWRDN = H enables the outputs.
D
7-0
R
IN
, G
IN
, B
IN
SCK
Zones of Uncertainty
D
7-0
R
IN
, G
IN
, B
IN
SCK
Zones of Serendipity
D
7-0
R
IN
, G
IN
, B
IN
SCK
Zones of Uncertainty
Figure 3. Internal Sampling Clock, SCK Timing
PHASE
Sn
PXCK/XCK
SCK
VIN
DCK
DA
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