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| 型號(hào)： | DSRT-L050-011 |
| 廠商： | CONEXANT SYSTEMS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, XMA |
| 文件頁數(shù)： | 49/76頁 |
| 文件大?。?/td> | 632K |
| 代理商： | DSRT-L050-011 |
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RipTide LP Audio/Comm System Product Description
1200
Conexant
53
Conexant Proprietary Information
PCI Bus Power Management Support
PCI Bus Power Management support consists primarily of the PCI configuration space interface, PME generation circuitry,
AMC’97 Codec Warm-reset generation circuitry and the ability of the Controller on-chip processor to manipulate the functional
state of various resources in the Controller and Codec.
PCI Configuration Space Interface
The following features exist in the PCI Configuration space of the Controller ’s three logical functions:
Capabilities List Indicator
Cap_Ptr
Capability ID
Next Capability Pointer
Power Management Capabilities Register
Power Management CSR
Data Register
In general, the Capabilities List Indicator, Cap_Ptr, Capability ID, Next Capability Pointer, Power Management Capabilities
Register and Data Register are used to report static power management information (information that does not change after
device enumeration) to the host processor. The Power Management CSR is used to control the device’s power management
state and to collect power management status information which may change over time.
Power State Support
Support for states D0 and D3 are required by the PCI Power Management specification V1.0. Support for D2 and D1 is
optional. After reset, the Audio Function (Function 0) supports D1 but not D2. The Modem Function (Function 1) and Joystick
Function (Function 2) support D2 but not D1.
The power state of a function is controlled by the host. At power-on/reset, all functions enter the D0 state. The host may then
place a function into another state by writing to the Power Management CSR. If the host attempts to force a function into an
unsupported state (as reported by the Power Management Capabilities register), the PCI transaction will complete normally,
but the value of the Power Management CSR will not be altered.
When the host writes a new (supported) value into the Power Management CSR, an interrupt is generated to the on-chip
processor. The on-chip processor is then responsible for taking whatever actions are necessary to implement the change of
power state.
Power Detection and Control
Specific GPIO pins of the controller have been programmed to function according to the chart below:
Pin name
Function
VAUXDET
Detects the presence of the Vaux supply. Connect to Vaux.
VPCIDET
Detects the presence of the Vpci supply. Connect to Vpci.
VAUXEN#
Controls an external FET to connect the controller VDD pins to Vaux. Active low
signal for use with a P-channel FET.
VPCIEN#
Controls an external FET to connect the controller VDD pins to Vpci. Active low
signal for use with a P-channel FET.
VPCIPREFFERED
If VPCIPREFFERED = 1, then Vaux is selected only if Modem Function (function
1) is in the D3 State and PME_en is true (1).
If VPCIPREFFERED = 0, then Vpci is selected only if Modem Function (function 1)
is in the D3 State and PME_en is false (0).
VPCIPREFFERED is established at reset as the value of GPIO1 when reset is
deasserted. VPCIPREFFERED cannot be changed except at reset.
To support a Power Management Event in D3cold, Vaux does not necessarily
need to be supplied to the Controller. With or without Vaux, PME in D3cold will be
detected as long as either +3.3 V or Vaux is supplied to the Controller.
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