- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄171235 > DSRT-L050-011 (CONEXANT SYSTEMS) SPECIALTY CONSUMER CIRCUIT, XMA PDF資料下載
參數(shù)資料
| 型號： | DSRT-L050-011 |
| 廠商： | CONEXANT SYSTEMS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, XMA |
| 文件頁數(shù)： | 43/76頁 |
| 文件大?。?/td> | 632K |
| 代理商： | DSRT-L050-011 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁當(dāng)前第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁
RipTide LP Audio/Comm System Product Description
48
Conexant
1200
Conexant Proprietary Information
AC-link Interface Description
The Controller implements an AC’97 compatible AC-link serial interface for connection with Conexant AMC’97 or MC’97
compliant combined audio/modem codec devices. AC-link is a 5-pin digital serial interface which supports time-multiplexed
transfer of command data/status and audio/modem stream sample data. The link is tied to a 48 kHz sample period. The
controller does not support the ‘double rate’ AC-Link feature.
For additional information on the AC-link Interface, refer to the AMC’97 Modem Codec Product Description (Order No. 1204).
7DEOH $&OLQN ,QWHUIDFH 6LJQDOV
Name
I/O
Description
BIT_CLK
I
12.288MHz Serial Bit Clock
SYNC
O
48 kHz Sample Period Synchronization
SDATA_OUT
O
Serial Data Out
SDATA_IN
I
Serial Data In
RESET#
O
Codec Reset.
AC-link Protocol
The BIT_CLK is driven by the Codec at 12.288 MHz. There are therefore 256 cycles of BIT_CLK in a 48 kHz sample period.
Transitions on the SYNC and SDATA_IN/SDATA_OUT signals occur coincidentally with the rising edges of BIT_CLK. These
signals should be sampled by their receiver on the next falling edge of BIT_CLK.
SYNC is driven by the Controller with a 48 kHz period. The waveform is high for 16 BIT_CLK cycles and low for the remaining
240 cycles.
An AC-link frame is defined to begin one clock period after the rising edge of SYNC. (i.e., at the rising edge of BIT_CLK
following the one at which SYNC transitioned from 0 to 1) The frame is divided into 13 slots, numbered 0 through 12, in the
order in which they are transmitted (12 is last). The first slot (0) is 16 BIT_CLK cycles long. The remaining 12 slots are each
20 BIT_CLK cycles long. The bit cycles within each slot are numbered from 15 to 0 (slot 0) or 19 to 0 (slots 1 through 12),
again in the order in which they are transmitted (0 is last).
AC'97
Digital Controller
AMC'97
Codec
SYNC
BIT_CLK
SDATA_OUT
SDATA_IN
RESET#
1200F13 AC-link
)LJXUH $&OLQN ,QWHUIDFH
Cold Reset
At power-up, the RESET# signal, which provides reset to the AMC’97 Codec, is held low for the appropriate amount of time
and then deasserted. Other portions of the controller will remain reset until the BIT_CLK signal has had enough time to
become active and the controller’s internal logic has had enough time to stabilize.
Warm Reset
An AMC’97 Warm Reset is supported by the controller.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DSS710D223S12-22 | 1 FUNCTIONS, 12 V, 7 A, DATA LINE FILTER |
| DST9HB32E101Q55J | 1 FUNCTIONS, 250 V, 6 A, DATA LINE FILTER |
| DST9HB32E220Q55J | 1 FUNCTIONS, 250 V, 6 A, DATA LINE FILTER |
| DST9HB32E222Q55J | 1 FUNCTIONS, 250 V, 6 A, DATA LINE FILTER |
| DST9HB32E271Q55J | 1 FUNCTIONS, 250 V, 6 A, DATA LINE FILTER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DSR-TSS-S1 | 制造商:DOMINANT 制造商全稱:DOMINANT Semiconductors 功能描述:Right Angle LED |
| DSR-TSS-S2 | 制造商:DOMINANT 制造商全稱:DOMINANT Semiconductors 功能描述:Right Angle LED |
| DSR-TSS-ST2-1 | 制造商:DOMINANT 制造商全稱:DOMINANT Semiconductors 功能描述:Right Angle LED |
| DSR-TSS-T1 | 制造商:DOMINANT 制造商全稱:DOMINANT Semiconductors 功能描述:Right Angle LED |
| DSR-TSS-T2 | 制造商:DOMINANT 制造商全稱:DOMINANT Semiconductors 功能描述:Right Angle LED |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。