All of the device pins (except V
參數(shù)資料
型號： DSPIC30F5015-30I/PT
廠商： Microchip Technology
文件頁數(shù)： 88/129頁
文件大?。?/td> 0K
描述： IC DSPIC MCU/DSP 66K 64TQFP
產(chǎn)品培訓模塊： dsPIC30F Quadrature Encoder Interface
Serial Communications using dsPIC30F CAN
Serial Communications using dsPIC30F I2C
Serial Communications using dsPIC30F SPI
Serial Communications using dsPIC30F UART
dsPIC30F 12 bit ADC - Part 2
dsPIC30F Addressing Modes - Part 1
dsPIC30F Architecture - Part 1
dsPIC30F DSP Engine & ALU
dsPIC30F Interrupts
dsPIC30F Motor Control PWM
dsPIC Timers
Asynchronous Stimulus
dsPIC30F Addressing Modes - Part 2
dsPIC30F Architecture - Part 2
dsPIC30F 12-bit ADC Part 1
標準包裝： 160
系列： dsPIC™ 30F
核心處理器： dsPIC
芯體尺寸： 16-位
速度： 30 MIP
連通性： CAN，I²C，SPI，UART/USART
外圍設(shè)備： 高級欠壓探測/復位，電機控制 PWM，QEI，POR，PWM，WDT
輸入/輸出數(shù)： 52
程序存儲器容量： 66KB（22K x 24）
程序存儲器類型： 閃存
EEPROM 大小： 1K x 8
RAM 容量： 2K x 8
電壓 - 電源 (Vcc/Vdd)： 2.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 16x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 64-TQFP
包裝： 托盤
產(chǎn)品目錄頁面： 651 (CN2011-ZH PDF)
配用： XLT64PT5-ND - SOCKET TRAN ICE 64MQFP/TQFP
AC164319-ND - MODULE SKT MPLAB PM3 64TQFP
DV164005-ND - KIT ICD2 SIMPLE SUIT W/USB CABLE
其它名稱： DSPIC30F501530IPT
2008 Microchip Technology Inc.
DS70149D-page 61
dsPIC30F5015/5016
8.0
I/O PORTS
All of the device pins (except VDD, VSS, MCLR and
OSC1/CLKI) are shared between the peripherals and
the parallel I/O ports.
All I/O input ports feature Schmitt Trigger inputs for
improved noise immunity.
8.1
Parallel I/O (PIO) Ports
When a peripheral is enabled and the peripheral is
actively driving an associated pin, the use of the pin as
a general purpose output pin is disabled. The I/O pin
may be read, but the output driver for the parallel port
bit will be disabled. If a peripheral is enabled, but the
peripheral is not actively driving a pin, that pin may be
driven by a port.
All port pins have three registers directly associated
with the operation of the port pin. The data direction
register (TRISx) determines whether the pin is an input
or an output. If the data direction bit is a ‘1’, then the pin
is an input. All port pins are defined as inputs after a
Reset. Reads from the latch (LATx), read the latch.
Writes to the latch, write the latch (LATx). Reads from
the port (PORTx), read the port pins and writes to the
port pins, write the latch (LATx).
Any bit and its associated data and control registers
that are not valid for a particular device will be
disabled. That means the corresponding LATx and
TRISx registers and the port pin will read as zeros.
When a pin is shared with another peripheral or
function that is defined as an input only, it is
nevertheless regarded as a dedicated port because
there is no other competing source of outputs. An
example is the INT4 pin.
The format of the registers for PORTA are shown in
The TRISA (Data Direction Control) register controls
the direction of the RA<7:0> pins, as well as the INTx
pins and the VREF pins. The LATA register supplies
data to the outputs and is readable/writable. Reading
the PORTA register yields the state of the input pins,
while writing the PORTA register modifies the contents
of the LATA register.
A parallel I/O (PIO) port that shares a pin with a
peripheral is, in general, subservient to the peripheral.
The peripheral’s output buffer data and control signals
are provided to a pair of multiplexers. The multiplexers
select whether the peripheral or the associated port
has ownership of the output data and control signals of
the I/O pad cell. Figure 8-2 shows how ports are shared
with other peripherals, and the associated I/O cell (pad)
to which they are connected. Table 8-1 and Table 8-2
show the formats of the registers for the shared ports,
PORTB through PORTG.
FIGURE 8-1:
BLOCK DIAGRAM OF A DEDICATED PORT STRUCTURE
Note:
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046). For more information on the
device instruction set and programming,
refer to the “dsPIC30F/33F Programmer’s
Reference Manual” (DS70157).
Q
D
CK
WR LAT+
TRIS Latch
I/O Pad
WR Port
Data Bus
Q
D
CK
Data Latch
Read LAT
Read Port
Read TRIS
WR TRIS
I/O Cell
Dedicated Port Module
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