參數(shù)資料
型號： DSPIC30F5015-30I/PT
廠商： Microchip Technology
文件頁數(shù)： 116/129頁
文件大小： 0K
描述： IC DSPIC MCU/DSP 66K 64TQFP
產(chǎn)品培訓模塊： dsPIC30F Quadrature Encoder Interface
Serial Communications using dsPIC30F CAN
Serial Communications using dsPIC30F I2C
Serial Communications using dsPIC30F SPI
Serial Communications using dsPIC30F UART
dsPIC30F 12 bit ADC - Part 2
dsPIC30F Addressing Modes - Part 1
dsPIC30F Architecture - Part 1
dsPIC30F DSP Engine & ALU
dsPIC30F Interrupts
dsPIC30F Motor Control PWM
dsPIC Timers
Asynchronous Stimulus
dsPIC30F Addressing Modes - Part 2
dsPIC30F Architecture - Part 2
dsPIC30F 12-bit ADC Part 1
標準包裝： 160
系列： dsPIC™ 30F
核心處理器： dsPIC
芯體尺寸： 16-位
速度： 30 MIP
連通性： CAN，I²C，SPI，UART/USART
外圍設備： 高級欠壓探測/復位，電機控制 PWM，QEI，POR，PWM，WDT
輸入/輸出數(shù)： 52
程序存儲器容量： 66KB（22K x 24）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量： 2K x 8
電壓 - 電源 (Vcc/Vdd)： 2.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 16x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 64-TQFP
包裝： 托盤
產(chǎn)品目錄頁面： 651 (CN2011-ZH PDF)
配用： XLT64PT5-ND - SOCKET TRAN ICE 64MQFP/TQFP
AC164319-ND - MODULE SKT MPLAB PM3 64TQFP
DV164005-ND - KIT ICD2 SIMPLE SUIT W/USB CABLE
其它名稱： DSPIC30F501530IPT
2008 Microchip Technology Inc.
DS70149D-page 87
dsPIC30F5015/5016
13.4.2
PWM PERIOD
The PWM period is specified by writing to the PRx
register. The PWM period can be calculated using
EQUATION 13-1:
PWM PERIOD
PWM frequency is defined as 1/[PWM period].
When the selected TMRx is equal to its respective
Period register, PRx, the following four events occur on
the next increment cycle:
TMRx is cleared.
The OCx pin is set.
- Exception 1: If PWM duty cycle is 0x0000,
the OCx pin will remain low.
- Exception 2: If duty cycle is greater than PRx,
the pin will remain high.
The PWM duty cycle is latched from OCxRS into
OCxR.
The corresponding timer interrupt flag is set.
See Figure 13-1 for key PWM period comparisons.
Timer3 is referred to in the figure for clarity.
FIGURE 13-1:
PWM OUTPUT TIMING
13.5
Output Compare Operation During
CPU Sleep Mode
When the CPU enters the Sleep mode, all internal
clocks are stopped. Therefore, when the CPU enters
the Sleep state, the output compare channel will drive
the pin to the active state that was observed prior to
entering the CPU Sleep state.
For example, if the pin was high when the CPU
entered the Sleep state, the pin will remain high.
Likewise, if the pin was low when the CPU entered the
Sleep state, the pin will remain low. In either case, the
output compare module will resume operation when
the device wakes up.
13.6
Output Compare Operation During
CPU Idle Mode
When the CPU enters the Idle mode, the output
compare module can operate with full functionality.
The output compare channel will operate during the
CPU Idle mode if the OCSIDL bit (OCxCON<13>) is at
logic ‘0’ and the selected time base (Timer2 or Timer3)
is enabled and the TSIDL bit of the selected timer is
set to logic ‘0’.
13.7
Output Compare Interrupts
The output compare channels have the ability to
generate an interrupt on a compare match, for
whichever match mode has been selected.
For all modes except the PWM mode, when a compare
event occurs, the respective interrupt flag (OCxIF) is
asserted and an interrupt will be generated, if enabled.
The OCxIF bit is located in the corresponding IFS
Status register and must be cleared in software. The
interrupt is enabled via the respective Compare
Interrupt
Enable
(OCxIE)
bit,
located
in
the
corresponding IEC Control register.
For the PWM mode, when an event occurs, the
respective Timer Interrupt Flag (T2IF or T3IF) is
asserted and an interrupt will be generated, if enabled.
The IF bit is located in the IFS0 Status register and
must be cleared in software. The interrupt is enabled
via the respective Timer Interrupt Enable bit (T2IE or
T3IE), located in the IEC0 Control register. The output
compare interrupt flag is never set during the PWM
mode of operation.
PWM Period = [(PRx) + 1] 4 TOSC
(TMRx Prescale Value)
Period
Duty Cycle
TMR3 = Duty Cycle (OCxR)
TMR3 = PR3
T3IF = 1
(Interrupt Flag)
OCxR = OCxRS
TMR3 = PR3
(Interrupt Flag)
OCxR = OCxRS
T3IF = 1
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