參數(shù)資料
型號(hào): DSPIC30F5015-30I/PT
廠商: Microchip Technology
文件頁數(shù): 69/129頁
文件大?。?/td> 0K
描述: IC DSPIC MCU/DSP 66K 64TQFP
產(chǎn)品培訓(xùn)模塊: dsPIC30F Quadrature Encoder Interface
Serial Communications using dsPIC30F CAN
Serial Communications using dsPIC30F I2C
Serial Communications using dsPIC30F SPI
Serial Communications using dsPIC30F UART
dsPIC30F 12 bit ADC - Part 2
dsPIC30F Addressing Modes - Part 1
dsPIC30F Architecture - Part 1
dsPIC30F DSP Engine & ALU
dsPIC30F Interrupts
dsPIC30F Motor Control PWM
dsPIC Timers
Asynchronous Stimulus
dsPIC30F Addressing Modes - Part 2
dsPIC30F Architecture - Part 2
dsPIC30F 12-bit ADC Part 1
標(biāo)準(zhǔn)包裝: 160
系列: dsPIC™ 30F
核心處理器: dsPIC
芯體尺寸: 16-位
速度: 30 MIP
連通性: CAN,I²C,SPI,UART/USART
外圍設(shè)備: 高級(jí)欠壓探測/復(fù)位,電機(jī)控制 PWM,QEI,POR,PWM,WDT
輸入/輸出數(shù): 52
程序存儲(chǔ)器容量: 66KB(22K x 24)
程序存儲(chǔ)器類型: 閃存
EEPROM 大小: 1K x 8
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 2.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-TQFP
包裝: 托盤
產(chǎn)品目錄頁面: 651 (CN2011-ZH PDF)
配用: XLT64PT5-ND - SOCKET TRAN ICE 64MQFP/TQFP
AC164319-ND - MODULE SKT MPLAB PM3 64TQFP
DV164005-ND - KIT ICD2 SIMPLE SUIT W/USB CABLE
其它名稱: DSPIC30F501530IPT
dsPIC30F5015/5016
DS70149D-page 44
2008 Microchip Technology Inc.
5.1
Interrupt Priority
The user-assignable Interrupt Priority (IP<2:0>) bits for
each individual interrupt source are located in the Least
Significant 3 bits of each nibble within the IPCx
register(s). Bit 3 of each nibble is not used and is read
as a ‘0’. These bits define the priority level assigned to
a particular interrupt by the user.
Since more than one interrupt request source may be
assigned to a specific user-assigned priority level, a
means is provided to assign priority within a given level.
This method is called “Natural Order Priority”.
Natural Order Priority is determined by the position of
an interrupt in the vector table, and only affects
interrupt operation when multiple interrupts with the
same user-assigned priority become pending at the
same time.
Table 5-1 lists the interrupt numbers and interrupt
sources for the dsPIC DSC devices and their
associated vector numbers.
The ability for the user to assign every interrupt to one
of seven priority levels means that the user can assign
a very high overall priority level to an interrupt with a
low natural order priority.
TABLE 5-1:
INTERRUPT VECTOR TABLE
Note:
The user-assignable priority levels start at
0, as the lowest priority and level 7, as the
highest priority.
Note 1: The Natural Order Priority scheme has 0
as the highest priority and 53 as the
lowest priority.
2: The Natural Order Priority number is the
same as the INT number.
Interrupt
Number
Vector
Number
Interrupt Source
Highest Natural Order Priority
0
8
INT0 – External Interrupt 0
1
9
IC1 – Input Capture 1
2
10
OC1 – Output Compare 1
3
11
T1 – Timer1
4
12
IC2 – Input Capture 2
5
13
OC2 – Output Compare 2
6
14
T2 – Timer2
7
15
T3 – Timer3
816
SPI1
9
17
U1RX – UART1 Receiver
10
18
U1TX – UART1 Transmitter
11
19
ADC – ADC Convert Done
12
20
NVM – NVM Write Complete
13
21
SI2C – I2C Slave Interrupt
14
22
MI2C – I2C Master Interrupt
15
23
Input Change Interrupt
16
24
INT1 – External Interrupt 1
17
25
Reserved
18
26
Reserved
19
27
OC3 – Output Compare 3
20
28
OC4 – Output Compare 4
21
29
T4 – Timer4
22
30
T5 – Timer5
23
31
INT2 – External Interrupt 2
24
32
Reserved
25
33
Reserved
26
34
SPI2
27
35
C1 – Combined IRQ for CAN1
28
36
IC3 – Input Capture 3
29
37
IC4 – Input Capture 4
30
38
Reserved
31
39
Reserved
32
40
Reserved
33
41
Reserved
34
42
Reserved
35
43
Reserved
36
44
INT3 – External Interrupt 3
37
45
INT4 – External Interrupt 4
38
46
Reserved
39
47
PWM – PWM Period Match
40
48
QEI – QEI Interrupt
41
49
Reserved
42
50
Reserved
43
51
FLTA – PWM Fault A
44
52
FLTB – PWM Fault B
45-53
53-61
Reserved
Lowest Natural Order Priority
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