參數(shù)資料
型號: DSPIC30F5015-30I/PT
廠商: Microchip Technology
文件頁數(shù): 43/129頁
文件大?。?/td> 0K
描述: IC DSPIC MCU/DSP 66K 64TQFP
產(chǎn)品培訓模塊: dsPIC30F Quadrature Encoder Interface
Serial Communications using dsPIC30F CAN
Serial Communications using dsPIC30F I2C
Serial Communications using dsPIC30F SPI
Serial Communications using dsPIC30F UART
dsPIC30F 12 bit ADC - Part 2
dsPIC30F Addressing Modes - Part 1
dsPIC30F Architecture - Part 1
dsPIC30F DSP Engine & ALU
dsPIC30F Interrupts
dsPIC30F Motor Control PWM
dsPIC Timers
Asynchronous Stimulus
dsPIC30F Addressing Modes - Part 2
dsPIC30F Architecture - Part 2
dsPIC30F 12-bit ADC Part 1
標準包裝: 160
系列: dsPIC™ 30F
核心處理器: dsPIC
芯體尺寸: 16-位
速度: 30 MIP
連通性: CAN,I²C,SPI,UART/USART
外圍設(shè)備: 高級欠壓探測/復位,電機控制 PWM,QEI,POR,PWM,WDT
輸入/輸出數(shù): 52
程序存儲器容量: 66KB(22K x 24)
程序存儲器類型: 閃存
EEPROM 大小: 1K x 8
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 2.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-TQFP
包裝: 托盤
產(chǎn)品目錄頁面: 651 (CN2011-ZH PDF)
配用: XLT64PT5-ND - SOCKET TRAN ICE 64MQFP/TQFP
AC164319-ND - MODULE SKT MPLAB PM3 64TQFP
DV164005-ND - KIT ICD2 SIMPLE SUIT W/USB CABLE
其它名稱: DSPIC30F501530IPT
dsPIC30F5015/5016
DS70149D-page 20
2008 Microchip Technology Inc.
2.3
Divide Support
The dsPIC DSC devices feature a 16/16-bit signed
fractional divide operation, as well as 32/16-bit and
16/16-bit signed and unsigned integer divide
operations, in the form of single instruction iterative
divides. The following instructions and data sizes are
supported:
1.
DIVF – 16/16 signed fractional divide
2.
DIV.sd – 32/16 signed divide
3.
DIV.ud – 32/16 unsigned divide
4.
DIV.sw – 16/16 signed divide
5.
DIV.uw – 16/16 unsigned divide
The divide instructions must be executed within a
REPEAT loop. Any other form of execution (e.g. a series
of discrete divide instructions) will not function correctly
because the instruction flow depends on RCOUNT. The
divide instruction does not automatically set up the
RCOUNT value, and it must, therefore, be explicitly and
correctly specified in the REPEAT instruction, as shown
in Table 2-1 (REPEAT will execute the target instruction
{operand value+1} times). The REPEAT loop count must
be set up for 18 iterations of the DIV/DIVF instruction.
Thus, a complete divide operation requires 19 cycles.
TABLE 2-1:
DIVIDE INSTRUCTIONS
2.4
DSP Engine
The DSP engine consists of a high-speed 17-bit x 17-bit
multiplier, a barrel shifter, and a 40-bit adder/subtracter
(with two target accumulators, round and saturation
logic).
The dsPIC30F devices have a single instruction flow
which can execute either DSP or MCU instructions.
Many of the hardware resources are shared between
the DSP and MCU instructions. For example, the
instruction set has both DSP and MCU multiply
instructions which use the same hardware multiplier.
The DSP engine also has the capability to perform
inherent accumulator-to-accumulator operations, which
require no additional data. These instructions are ADD,
SUB and NEG.
The DSP engine has various options selected through
various bits in the CPU Core Configuration register
(CORCON), as listed below:
Fractional or Integer DSP Multiply (IF)
Signed or Unsigned DSP Multiply (US)
Conventional or Convergent Rounding (RND)
Automatic Saturation On/Off for ACCA (SATA)
Automatic Saturation On/Off for ACCB (SATB)
Automatic Saturation On/Off for Writes to Data
Memory (SATDW)
Accumulator Saturation mode Selection
(ACCSAT)
A block diagram of the DSP engine is shown in
Note:
The divide flow is interruptible. However,
the user needs to save the context as
appropriate.
Instruction
Function
DIVF
Signed fractional divide: Wm/Wn
→ W0; Rem → W1
DIV.sd
Signed divide: (Wm+1:Wm)/Wn
→ W0; Rem → W1
DIV.ud
Unsigned divide: (Wm+1:Wm)/Wn
→ W0; Rem → W1
DIV.sw
Signed divide: Wm/Wn
→ W0; Rem → W1
DIV.uw
Unsigned divide: Wm/Wn
→ W0; Rem → W1
Note:
For CORCON layout, see Table 3-3.
TABLE 2-2:
DSP INSTRUCTION
SUMMARY
Instruction
Algebraic Operation
CLR
A = 0
ED
A = (x - y)2
EDAC
A = A + (x - y)2
MAC
A = A + (x * y)
MOVSAC
No change in A
MPY
A = x * y
MPY.N
A = - x * y
MSC
A = A - x * y
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