參數(shù)資料
型號: DSPB56007FJ66
英文描述: DSP|24-BIT|CMOS|QFP|80PIN|PLASTIC
中文描述: 數(shù)字信號處理器| 24位|的CMOS | QFP封裝| 80腳|塑料
文件頁數(shù): 57/83頁
文件大?。?/td> 382K
代理商: DSPB56007FJ66
Specifications
Serial Host Interface (SHI) I
2
C Protocol Timing
MOTOROLA
DSP56007/D
2-33
174 Start Condition
Hold Time
t
HD;STA
master
slave
bypassed
narrow
wide
bypassed
narrow
wide
0.5
×
t
I
2
CCP
+
12 – t
f
0.5
×
t
I
2
CCP
+
12 – t
f
0.5
×
t
I
2
CCP
+
12 – t
f
2
×
T
C
+ T
H
+ 21
2
×
T
C
+ T
H
+ 100
2
×
T
C
+ T
H
+ 200
0.5
×
t
I
18 – t
f
0.5
×
t
I
18 – t
f
0.5
×
t
I
18 – t
f
2
×
T
C
+ 74 + t
r
2
×
T
C
+ 286 + t
r
2
×
T
C
+ 586 + t
r
0.5
×
t
I
T
C
+ 19
0.5
×
t
I
2
×
T
C
+ 144
0.5
×
t
I
2
×
T
C
+ 356
2
×
T
C
+ T
H
– 1
2
×
T
C
+ T
H
+ 18
2
×
T
C
+ T
H
+ 30
332
352
372
71
150
250
318
340
378
59
138
238
310
333
367
49.4
128
228
ns
ns
ns
ns
ns
ns
175 SCL Low Period
t
LOW
master
slave
bypassed
narrow
wide
bypassed
narrow
wide
2
CCP
+
2
CCP
+
2
CCP
+
338
358
378
352
564
864
324
346
384
342
554
854
316
339
373
335
534
847
ns
ns
ns
ns
ns
ns
176 SCL High Period
t
HIGH
master
slave
bypassed
narrow
wide
bypassed
narrow
wide
2
CCP
+ 2
×
2
CCP
+
2
CCP
+
379
544
776
49
68
80
375
523
773
37
56
68
360
507
754
27.4
46.4
58.4
ns
ns
ns
ns
ns
ns
177
SCL Rise Time
Output
1
Input
t
r
1.7
×
R
P
×
(C
L
+ 20)
2000
238
2000
238
2000
238
2000
ns
ns
178 SCL Fall Time
Output
1
Input
t
f
20 + 0.1
×
(C
L
– 50)
2000
20
2000
20
2000
20
2000
ns
ns
179 Data Set-up Time t
SU;DAT
bypassed
narrow
wide
T
C
+ 8
T
C
+ 60
T
C
+ 74
28
80
94
23
75
89
19.4
71.4
85.4
ns
ns
ns
Table 2-15
SHI Improved I
2
C Protocol Timing (Continued)
Improved I
2
C (C
L
= 50 pF, R
P
= 2 k
)
No.
Char.
Sym.
Mode
Filter
Mode
Expression
50 MHz
2
66 MHz
3
88 MHz
4
U
n
i
t
Min Max Min Max Min Max
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