參數(shù)資料
型號： DSPB56007FJ66
英文描述： DSP|24-BIT|CMOS|QFP|80PIN|PLASTIC
中文描述： 數(shù)字信號處理器| 24位|的CMOS | QFP封裝| 80腳|塑料
文件頁數(shù)： 49/83頁
文件大?。?/td> 382K
代理商： DSPB56007FJ66
Specifications
Serial Host Interface (SHI) SPI Protocol Timing
MOTOROLA
DSP56007/D
2-25
153 SCK Edge to Data Out
Not Valid
(Data Out Hold Time)
master
slave
bypassed
narrow
wide
bypassed
narrow
wide
0
57
163
0
57
163
0
57
163
0
57
163
—
—
—
—
—
—
0
57
163
0
57
163
—
—
—
—
—
—
0
57
163
0
57
163
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
154 SS Assertion to Data Out
Valid CPHA = 0
slave
T
C
+ T
H
+ 35
—
65
—
58
—
52.0
ns
157 First SCK Sampling
Edge to HREQ Output
Deassertation
slave
bypassed
narrow
wide
3
×
T
C
+ T
H
+ 32
3
×
T
C
+ T
H
+ 209
3
×
T
C
+ T
H
+ 507
2
×
T
C
+ T
H
+ 6
2
×
T
C
+ T
H
+ 63
2
×
T
C
+ T
H
+ 169
—
—
—
102
279
577
—
—
—
85
262
560
—
—
—
71.8
248.8
546.8
ns
ns
ns
158 Last SCK Sampling Edge
to HREQ Output Not
Deasserted
CPHA = 1
slave
bypassed
narrow
wide
56
113
219
—
—
—
44
101
207
—
—
—
34.4
91.4
197.4
—
—
—
ns
ns
ns
159 SS Deassertation to
HREQ Output Not
Deasserted
CPHA = 0
slave
2
×
T
C
+ T
H
+ 7
57
45
35.4
ns
160 SS Deassertation Pulse
Width CPHA = 0
slave
T
C
+ 4
24
—
19
—
15.4
—
ns
161 HREQ In Assertion to
First SCK Edge
master
0.5
×
t
SPICC
+
2
×
T
C
+ 6
0
106
—
82
—
62.8
—
ns
162 HREQ In Deassertation
to Last SCK Sampling
Edge (HREQ In Set-up
Time) CPHA = 1
master
0
—
0
—
0
—
ns
163 First SCK Edge to HREQ
In Not Asserted
(HREQ In Hold Time)
master
0
0
—
0
—
0
—
ns
Note:
1.
For an Internal Clock frequency below 33 MHz, the minimum permissible Internal Clock to Serial Clock frequency
ratio is 4:1. For an Internal Clock frequency above 33 MHz, the minimum permissible Internal Clock to Serial
Clock frequency ratio is 6:1.
In CPHA = 1 mode, the SPI slave supports data transfers at t
SPICC
= 3
×
T
C
, if the user assures that the HTX is
written at least
T
C
ns before the first edge of SCK of each word.In CPHA = 1 mode, the SPI slave supports data
transfers at t
SPICC
= 3
×
T
C
, if the user assures that the HTX is written at least
T
C
ns before the first edge of
SCK of each word.
When CPHA = 1, the SS line may remain active low between successive transfers.
Periodically sampled, not 100% tested
Refer to the
DSP56007 User’s Manual
for a detailed description of how to use the different filtering
modes.
2.
3.
4.
5.
Table 2-12
Serial Host Interface (SHI) SPI Protocol Timing (Continued)
No.
Characteristics
Mode
Filter
Mode
Expression
50 MHz
66 MHz
88 MHz
Unit
Min Max Min Max
Min
Max
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