參數(shù)資料
型號： DSPB56007FJ66
英文描述： DSP|24-BIT|CMOS|QFP|80PIN|PLASTIC
中文描述： 數(shù)字信號處理器| 24位|的CMOS | QFP封裝| 80腳|塑料
文件頁數(shù)： 12/83頁
文件大小： 382K
代理商： DSPB56007FJ66
1-6
DSP56007/D
MOTOROLA
Signal/Connection Descriptions
External Memory Interface (EMI)
.
MD0–MD7
Bidi-
rectional
Tri-stated
Data Bus
—These signals provide the bidirectional data bus for
EMI accesses. They are inputs during reads from external
memory, outputs during writes to external memory, and tri-
stated if no external access is taking place. If the data bus width
is defined as four bits wide, only signals MD0–MD3 are active,
while signals MD4–MD7 remain tri-stated. While tri-stated,
MD0–MD7 are disconnected from the pins and do not require
external pull-ups.
Table 1-6
EMI States during Reset and Stop States
Signal
Operating Mode
Hardware Reset
Software Reset Individual Reset
Stop Mode
MA0–MA14
Driven High
Previous State
Previous State
Previous State
MA15
MCS3
Driven High
Driven High
Driven High
Driven High
Previous State
Driven High
Previous State
Driven High
MA16
MCS2
MCAS:
DRAM refresh disabled
DRAM refresh enabled
Driven High
Driven High
Driven High
Driven High
Driven High
Driven High
Driven High
Driven High
Previous State
Driven High
Driven High
Driven Low
Previous State
Driven High
Driven High
Driven High
MA17
MCS1
MRAS
:
DRAM refresh disabled
DRAM refresh enabled
Driven High
Driven High
Driven High
Driven High
Driven High
Driven High
Driven High
Driven High
Previous State
Driven High
Driven High
Driven Low
Previous State
Driven High
Driven High
Driven High
MCS0
Driven High
Driven High
Driven High
Driven High
MWR
Driven High
Driven High
Driven High
Driven High
MRD
Driven High
Driven High
Driven High
Driven High
Table 1-5
External Memory Interface (EMI) Signals (Continued)
Signal Name
Signal
Type
State during
Reset
Signal Description
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