參數資料
型號: DSPB56007FJ66
英文描述: DSP|24-BIT|CMOS|QFP|80PIN|PLASTIC
中文描述: 數字信號處理器| 24位|的CMOS | QFP封裝| 80腳|塑料
文件頁數: 34/83頁
文件大小: 382K
代理商: DSPB56007FJ66
2-10
DSP56007/D
MOTOROLA
Specifications
External Memory Interface (EMI) DRAM Timing
54 CAS Deassertation Pulse
Width
(Page Mode Access
Only)
55 Row Address Valid to
RAS Assertion
(Row Address Setup
Time)
56 RAS Assertion to ROW
Address Not Valid
(Row Address Hold
Time)
57 Column Address Valid
to CAS Assertion
(Column Address Setup
Time)
58 CAS Assertion to
Column Address Not
Valid
(Column Address Hold
Time)
59 Last CAS Assertion to
Column Address Not
Valid (Column Address
Hold Time)
60 RAS Assertion to
Column Address Not
Valid
T
CP
T
C
– 5
15
10
6.4
ns
t
ASR
T
L
– 6
4
2
0.1
ns
t
RAH
slow
fast
3
×
T
C
+ T
H
14
2
×
T
C
+ T
H
14
T
L
– 6
56
36
39
24
25.8
14.4
ns
ns
t
ASC
4
2
0.1
ns
T
CAH
slow
fast
3
×
T
C
+ T
H
14
2
×
T
C
+ T
H
14
56
36
39
24
25.8
14.4
ns
ns
T
CAH
slow
fast
7
×
T
C
+ T
H
14
4 ×
T
C
+ T
H
14
7
×
T
C
+ T
H
14
5
×
T
C
+ T
H
14
3
×
T
C
+ T
L
7
2
×
T
C
+ T
L
7
5
×
T
C
– 11
3
×
T
C
– 11
136
76
100
54
71.2
37.1
ns
ns
t
AR
slow
fast
136
96
100
69
71.2
48.5
ns
ns
61 Column Address Valid
to RAS Deassertation
t
RAL
slow
fast
63
43
46
30
32.8
21.2
ns
ns
62 CAS, RAS, RD, or WR
Deassertation to WR or
RD Assertion
63 CAS or RD
Deassertation to Data
Not Valid
(Data Hold Time)
t
RCH
,
t
RRH
slow
fast
89
49
65
35
45.8
23.1
ns
ns
t
OFF
,
t
GZ
0
0
0
0
ns
Table 2-8
External Memory Interface (EMI) DRAM Timing (Continued)
No.
Characteristics
Symbol
Timing
Mode
Expression
50 MHz
66 MHz
88 MHz
Unit
Min Max Min Max Min Max
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