
Reset, Stop, Wait, Mode Select, and Interrupt Timing
56F827 Technical Data
31
Figure 16. Asynchronous Reset Timing
IRQA Low to First Valid Interrupt Vector Address Out
recovery from Wait State
3
t
IRI
13T
—
ns
Figure 19
IRQA Width Assertion to Recover from Stop State
4
t
IW
2T
—
ns
Figure 20
Delay from IRQA Assertion to Fetch of first instruction
(exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
t
IF
—
—
275,000T
12T
ns
ns
Figure 20
Duration for Level Sensitive IRQA Assertion to Cause
the Fetch of First IRQA Interrupt Instruction (exiting
Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
t
IRQ
—
—
275,000T
12T
ns
ns
Figure 21
Delay from Level Sensitive IRQA Assertion to First
Interrupt Vector Address Out Valid (exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
t
II
—
—
275,000T
12T
ns
ns
Figure 21
1.
2.
In the formulas, T = clock cycle. For an operating frequency of 80MHz, T = 12.5ns.
Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases:
After power-on reset
When recovering from Stop state
The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state.
This is not the minimum required so that the IRQA interrupt is accepted.
4.
The interrupt instruction fetch is visible on the pins only in Mode 3.
5.
Parameters listed are guaranteed by design.
3.
Table 14. Reset, Stop, Wait, Mode Select, and Interrupt Timing
1, 5
(Continued)
Operating Conditions:
V
SSIO
=V
SS
= V
SSA
= 0V, V
DDA
=V
DDIO
=3.0–3.6V, V
DD
= 2.25–2.75V, T
A
= –40
°
to +85
°
C, C
L
≤
50pF, f
op
= 80MHz
Characteristic
Symbol
Min
Max
Unit
See
Figure
First Fetch
A0–A15,
D0–D15
PS, DS,
RD, WR
RESET
First Fetch
t
RA
t
RAZ
t
RDA
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.