參數(shù)資料
型號： DSP56F827
廠商： 飛思卡爾半導體(中國)有限公司
英文描述： 16-bit Hybrid Controller(16位混合控制器)
中文描述： 16位混合控制器（16位混合控制器）
文件頁數(shù)： 11/52頁
文件大?。?/td> 1175K
代理商： DSP56F827
Signals and Package Information
56F827 Technical Data
11
DS
(PCS1)
17
Output
Data Memory Select
—DS is asserted low for external Data memory
access. This pin can also be programmed as a programmable chip
select.
RD
15
Output
Read Enable
—RD is asserted during external memory read cycles.
When RD is asserted low, pins D0–D15 become inputs and an external
device is enabled onto the device data bus. When RD is deasserted
high, the external data is latched inside the device. When RD is
asserted, it qualifies the A0–A15, PS, and DS pins. RD can be
connected directly to the OE pin of a Static RAM or ROM.
WR
16
Output
Write Enable
—WR is asserted during external memory write cycles.
When WR is asserted low, pins D0–D15 become outputs and the
device puts data on the bus. When WR is deasserted high, the external
data is latched inside the external device. When WR is asserted, it
qualifies the A0–A15, PS, and DS pins. WR can be connected directly
to the WE pin of a Static RAM.
TA0
(GPIOF0)
112
Input/Output
Input/Output
TA0–3
—Timer A Channels 0, 1, 2, and 3
Port F GPIO
—These four General Purpose I/O (GPIO) pins can be
individually programmed as input or output.
After reset, the default state is Quad Timer.
TA1
(GPIOF1)
111
TA2
(GPIOF2)
110
TA3
(GPIOF3)
109
TCK
44
Input
(Schmitt)
Test Clock Input
—This input pin provides a gated clock to synchronize
the test logic and shift serial data to the JTAG/OnCE port. The pin is
connected internally to a pull-down resistor.
TMS
46
Input
(Schmitt)
Test Mode Select Input
—This input pin is used to sequence the JTAG
TAP controller’s state machine. It is sampled on the rising edge of TCK
and has an on-chip pull-up resistor.
TDI
48
Input
(Schmitt)
Test Data Input
—This input pin provides a serial input data stream to
the JTAG/OnCE port. It is sampled on the rising edge of TCK and has
an on-chip pull-up resistor.
TDO
47
Input/Output
Test Data Output
—This tri-statable output pin provides a serial output
data stream from the JTAG/OnCE port. It is driven in the Shift-IR and
Shift-DR controller states, and changes on the falling edge of TCK.
TRST
45
Input
(Schmitt)
Test Reset
—As an input, a low signal on this pin provides a reset
signal to the JTAG TAP controller. To ensure complete hardware reset,
TRST should be asserted whenever RESET is asserted. The only
exception occurs in a debugging environment when a hardware device
reset is required and it is necessary not to reset the JTAG/OnCE
module. In this case, assert RESET, but do not assert TRST. TRST
must always be asserted at power-up.
DE
41
Output
Debug Event
—DE provides a low pulse on recognized debug events.
Table 3. 56F827 Signal and Package Information for the 128 Pin LQFP (Continued)
Signal Name
Pin No.
Type
Description
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
相關PDF資料
PDF描述
DSP8-08AC Phase-leg Rectifier Diode ISOPLUS220
DSP8-08 Phase-leg Rectifier Diode
DSP8-08AS Phase-leg Rectifier Diode
DSP8-08S Phase-leg Rectifier Diode
DSP8-12S Phase-leg Rectifier Diode
相關代理商/技術參數(shù)
參數(shù)描述
DSP56F827/D 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:56F827 16-bit Hybrid Controller
DSP56F827E 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers
DSP56F827E/D 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:56F827 16-bit Hybrid Controller
DSP56F827EVM 制造商:Freescale Semiconductor 功能描述:Microprocessor Support IC For Use With:5
DSP56F827EVMUM 制造商:未知廠家 制造商全稱:未知廠家 功能描述:56F827 Evaluation Module Hardware User＇s Manual
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*