參數(shù)資料
型號(hào)： DSP56F827
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： 16-bit Hybrid Controller(16位混合控制器)
中文描述： 16位混合控制器（16位混合控制器）
文件頁(yè)數(shù)： 16/52頁(yè)
文件大?。?/td> 1175K
代理商： DSP56F827
16
56F827 Technical Data
Part 3 Specifications
3.1 General Characteristics
The 56F827 is fabricated in high-density CMOS with 5V-tolerant TTL-compatible digital inputs. The term
“5V-tolerant” refers to the capability of an I/O pin, built on a 3.3V-compatible process technology, to
withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices
designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V- and 5V-compatible
I/O voltage levels. A standard 3.3V I/O is designed to receive a maximum voltage of 3.3V
±
10% during
V
REFMID
68
Input
ADC Reference
—This pin isconnected to the center of the ADC input
range. This pin requires a 0.1
μ
F ceramic capacitor to V
SSA
and a start-
up time of 25ms, prior to beginning conversions.
V
REFLO
64
Input
ADC Reference
—These pins are Negative Reference for ADC and are
generally connected to a V
SSA
.
V
REFHI
67
Input
ADC Reference
—These pins are Positive Reference for ADC and are
generally connected to a 3.3V Analog (V
DDA_ADC)
supply.
IRQA
40
Input
(Schmitt)
External Interrupt Request A
—The IRQA input is a synchronized
external interrupt request that indicates that an external device is
requesting service. It can be programmed to be level-sensitive or
negative-edge-triggered. If level-sensitive triggering is selected, an
external pull-up resistor is required for wired-OR operation.
If the processor is in the Stop state and IRQA is asserted, the processor
will exit the Stop state.
IRQB
49
Input
(Schmitt)
External Interrupt Request B
—The IRQB input is an external interrupt
request that indicates that an external device is requesting service. It
can be programmed to be level-sensitive or negative-edge-triggered. If
level-sensitive triggering is selected, an external pull-up resistor is
required for wired-OR operation.
RESET
42
Input
(Schmitt)
Reset
—This input is a direct hardware reset on the processor. When
RESET is asserted low, the device is initialized and placed in the Reset
state. A Schmitt trigger input is used for noise immunity. When the
RESET pin is deasserted, the initial chip operating mode is latched from
the external boot pin. The internal reset signal will be deasserted
synchronous with the internal clocks, after a fixed number of internal
clocks.
To ensure complete hardware reset, RESET and TRST should be
asserted together. The only exception occurs in a debugging
environment when a hardware device reset is required and it is
necessary not to reset the OnCE/JTAG module. In this case, assert
RESET, but do not assert TRST.
EXTBOOT
39
Input
(Schmitt)
External Boot
—This input is tied to V
DD
to force device to boot from
off-chip memory. Otherwise, it is tied to V
SS
.
Table 3. 56F827 Signal and Package Information for the 128 Pin LQFP (Continued)
Signal Name
Pin No.
Type
Description
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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相關(guān)代理商/技術(shù)參數(shù)
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DSP56F827/D 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:56F827 16-bit Hybrid Controller
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DSP56F827E/D 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:56F827 16-bit Hybrid Controller
DSP56F827EVM 制造商:Freescale Semiconductor 功能描述:Microprocessor Support IC For Use With:5
DSP56F827EVMUM 制造商:未知廠家 制造商全稱:未知廠家 功能描述:56F827 Evaluation Module Hardware User＇s Manual
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