參數(shù)資料
型號(hào): DS33Z11
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 網(wǎng)絡(luò)接口
英文描述: Ethernet Mapper
中文描述: DATACOM, NETWORK INTERFACE SUPPORT CIRCUIT, PBGA169
封裝: 14 X 14 MM, 1 MM PITCH, CSBGA-169
文件頁數(shù): 80/169頁
文件大小: 1049K
代理商: DS33Z11
DS33Z11 Ethernet Mapper
9.3 Arbiter Registers
80 of 169
The Arbiter manages the transport between the Ethernet port and the Serial Interface. It is responsible for queuing
and dequeuing data to an external SDRAM. The arbiter handles requests from the HDLC and MAC to transfer
data to/from the SDRAM. The base address of the Arbiter register space is 0040h.
9.3.1 Arbiter Register Bit Descriptions
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
AR.RQSC1
Arbiter Receive Queue Size Connection
40h
7
6
5
4
3
2
1
0
RQSC7
0
RQSC6
0
RQSC5
1
RQSC4
1
RQSC3
1
RQSC2
1
RQSC1
0
RQSC0
1
Bits 0-7: Receive Queue Size (RQSC[0:7])
These 7 bits of the size of receive queue associated with the
connection. Receive queue is for data arriving from the MAC to be sent to the WAN. The Queue address size is
defined in increments of 32 x 2048 bytes. The queue size is AR.RQSC1 multiplied by 32 to determine the number
of 2048 byte packets that can be stored in the queue. This queue is constructed in the external SDRAM
. Note:
Queue size of 0 is not allowed and should never be set.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
AR.TQSC1
Arbiter Transmit Queue Size Connection 1
41h
7
6
5
4
3
2
1
0
TQSC7
0
TQSC6
0
TQSC5
0
TQSC4
0
TQSC3
0
TQSC2
0
TQSC1
1
TQSC0
1
Bits 0-7: Transmit Queue Size (TQSC[0:7])
This is size of transmit queue associated with the connection. The
queue address size is defined in increments of 32 packets. The range of bytes will depend on the external SDRAM
connected to the DS33Z11. Transmit queue is the data queue for data arriving on the WAN that is sent to the
MAC.
Note that queue size of 0 is not allowed and should never be set.
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