參數(shù)資料
型號: DS33Z11
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 網(wǎng)絡(luò)接口
英文描述: Ethernet Mapper
中文描述: DATACOM, NETWORK INTERFACE SUPPORT CIRCUIT, PBGA169
封裝: 14 X 14 MM, 1 MM PITCH, CSBGA-169
文件頁數(shù): 31/169頁
文件大?。?/td> 1049K
代理商: DS33Z11
DS33Z11 Ethernet Mapper
31 of 169
8.3 CLOCK STRUCTURE
The DS33Z11 clocks sources and functions are as follows:
Serial Transmit Data (TCLKI) and Serial Receive Data (RCLKI) clock inputs are used to transfer data from
the serial interface. These clocks can be continuous or gapped.
System Clock (SYSCLKI) input. Used for internal operation. This clock input cannot be a gapped clock. A
clock supply with ±100 ppm frequency accuracy is suggested. A buffered version of this clock is provided
on the SDCLKO pin for the operation of the SDRAM. A divided and buffered version of this clock is
provided on the SPICK pin for Serial EEPROM operation. A divided and buffered version of this clock is
provided on REF_CLKO for the RMII/MII interface.
Packet Interface Reference clock (REF_CLK) input that can be 25 or 50 MHz. This clock is used as the
timing reference for the RMII/MII interface. The user can utilize the built-in REF_CLKO output clock to
drive this input.
The Transmit and Receive clocks for the MII Interface (TX_CLK and RX_CLK). In DTE mode, these are
input pins and accept clocks provided by an Ethernet PHY. In the DCE mode, these are output pins and
will output an internally generated clock to the Ethernet PHY. The output clocks are generated by internal
division of REF_CLK. In RMII mode, only the REF_CLK input is used.
REF_CLKO is an output clock that is generated by dividing the 100 MHz System clock (SYSCLKI) by 2 or
4. This output clock can be used as an input to REF_CLK, allowing the user to have one less oscillator for
the system.
A Management Data Clock (MDC) output is derived from SYSCLKI and is used for information transfer
between the internal Ethernet MAC and external PHY. The MDC clock frequency is 1.67 MHz.
The following table provides the different clocking options for the Ethernet interface.
Table 8-1 Clocking Options for the Ethernet Interface
RMIIMIIS
Pin
Speed
DCE/
DTE
REF_CLKO
Output
REF_CLK
Input
25 MHz
+/- 100 ppm
25 MHz
+/- 100 ppm
25 MHz
+/- 100 ppm
50 MHz
+/- 100 ppm
50 MHz
+/- 100 ppm
RX_CLK
TX_CLK
MDC
Output
0 (MII)
10
Mbps
10
Mbps
100
Mbps
10
Mbps
100
Mbps
DTE
25 MHz
Input from
PHY
2.5 MHz
(Output)
25 MHz
(Output)
Input from
PHY
2.5 MHz
(Output)
25 MHz
(Output)
1.67 MHz
0 (MII)
DCE
25 MHz
1.67 MHz
0 (MII)
DCE
25 MHz
1.67 MHz
1 (RMII)
-
50 MHz
Not Applicable
Not Applicable
1.67 MHz
1 (RMII)
-
50 MHz
Not Applicable
Not Applicable
1.67 MHz
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DS33Z41DK 功能描述:以太網(wǎng)開發(fā)工具 DS33Z41 Dev Kit RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評估:KSZ8873RLL 接口類型:RMII 工作電源電壓: