參數(shù)資料
型號: DS33Z11
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 網(wǎng)絡(luò)接口
英文描述: Ethernet Mapper
中文描述: DATACOM, NETWORK INTERFACE SUPPORT CIRCUIT, PBGA169
封裝: 14 X 14 MM, 1 MM PITCH, CSBGA-169
文件頁數(shù): 108/169頁
文件大?。?/td> 1049K
代理商: DS33Z11
DS33Z11 Ethernet Mapper
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
108 of 169
LI.RHPMUU
Serial Interface Receive HDLC PMU Update Register
120h
6
5
4
-
-
-
0
0
0
7
-
0
3
-
0
2
-
0
1
-
0
0
RPMUU
0
Bit 0: Receive PMU Update (RPMUU)
This signal causes the receive cell/packet processor block performance
monitoring registers (counters) to be updated. A 0 to 1 transition causes the performance monitoring registers to
be updated with the latest data, and the counters reset (0 or 1). This update updates performance-monitoring
counters for the Serial Interface.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
LI.RHPMUS
Serial Interface Receive HDLC PMU Update Status Register
121h
6
5
4
-
-
-
0
0
0
7
-
0
3
-
0
2
-
0
1
-
0
0
RPMUUS
0
Bit 0: Receive PMU Update Status (RPMUUS)
This bit is set when the Transmit PMU Update is completed. This
bit is cleared when RPMUU is set to 0.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 3:
SAPI High is not equal to LI.TRX86SAPIH Latched Status
(SAPIHNE)
This latched status bit is set if
SAPIH is not equal to LI.TRX86SAPIH. This latched status bit is cleared upon read.
LI.RX86S
Receive X.86 Latched Status Register
122h
7
-
-
6
-
-
5
-
-
4
-
-
3
2
1
0
SAPIHNE
-
SAPILNE
-
CNE
-
ANE
-
Bit 2:
SAPI Low is not equal to LI.TRX86SAPIL Latched Status
(SAPILNE)
This latched status bit is set if
SAPIL is not
equal to LI.TRX86SAPIL. This latched status bit is cleared upon read.
Bit 1: Control is not equal to LI.TRX8C (CNE)
This latched status bit is set if the control field is not equal to
LI.TRX8C
. This latched status bit is cleared upon read.
Bit 0: Address is not equal to LI.TRX86A (ANE)
This latched status bit is set if the X.86 Address field is not
equal to
LI.TRX86A
. This latched status bit is cleared upon read.
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