參數(shù)資料
型號: DS33Z11
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 網(wǎng)絡(luò)接口
英文描述: Ethernet Mapper
中文描述: DATACOM, NETWORK INTERFACE SUPPORT CIRCUIT, PBGA169
封裝: 14 X 14 MM, 1 MM PITCH, CSBGA-169
文件頁數(shù): 110/169頁
文件大?。?/td> 1049K
代理商: DS33Z11
DS33Z11 Ethernet Mapper
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
110 of 169
LI.TQHT
Serial Interface Transmit Queue High Threshold (Watermark)
125h
7
6
5
4
3
2
1
0
TQHT7
0
TQHT6
0
TQHT5
0
TQHT4
0
TQHT3
0
TQHT2
0
TQHT1
0
TQHT0
0
Bits 0 – 7: Transmit Queue High Threshold (TQHT[0:7])
The transmit
queue high threshold for the connection,
in increments of 32 packets of 2048 bytes each. The value of this register is multiplied by 32 * 2048 bytes to
determine the byte location of the threshold. Note that the transmit queue is for data that was received from the
Serial Interface to be sent to the Ethernet Interface.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
LI.TQTIE
Serial Interface Transmit Queue Cross Threshold Interrupt Enable
126h
7
-
0
6
-
0
5
-
0
4
-
0
3
2
1
0
TFOVFIE
0
TQOVFIE
0
TQHTIE
0
TQLTIE
0
Bit 3: Transmit FIFO Overflow for Connection Interrupt Enable (TFOVFIE)
If this bit is set, the watermark
interrupt is enabled for TFOVFLS.
Bit 2: Transmit Queue Overflow for Connection Interrupt Enable (TQOVFIE)
If this bit is set, the watermark
interrupt is enabled for TQOVFLS.
Bit 1: Transmit Queue for Connection High Threshold Interrupt Enable (TQHTIE)
If this bit is set, the
watermark interrupt is enabled for TQHTS.
Bit 0: Transmit Queue for Connection Low Threshold Interrupt Enable (TQLTIE)
If this bit is set, the
watermark interrupt is enabled for TQLTS.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
LI.TQCTLS
Serial Interface Transmit Queue Cross Threshold Latched Status
127h
7
-
-
6
-
-
5
-
-
4
-
-
3
2
1
0
TFOVFLS
-
TQOVFLS
-
TQHTLS
-
TQLTLS
-
Bit 3: Transmit Queue FIFO Overflowed Latched Status (TFOVFLS)
This bit is set if the transmit queue FIFO
has overflowed. This register is cleared after a read. This FIFO is for data to be transmitted from the HDLC to be
sent to the SDRAM.
Bit 2: Transmit Queue Overflow Latched Status (TQOVFLS)
This bit is set if the transmit queue has
overflowed. This register is cleared after a read.
Bit 1: Transmit Queue for Connection Exceeded High Threshold Latched Status (TQHTLS)
This bit is set if
the transmit queue crosses the High Watermark. This register is cleared after a read.
Bit 0: Transmit Queue for Connection Exceeded Low Threshold Latched Status (TQLTLS)
This bit is set if
the transmit queue crosses the Low Watermark. This register is cleared after a read.
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